[U-Boot] [PATCH 1/4] rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock

[Philipp Tomsich]

Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.

Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
---

 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
index 216a26c..4dd84e2 100644
--- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
@@ -5,6 +5,7 @@
  *
  * Adapted from coreboot.
  */
+
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
@@ -19,6 +20,7 @@
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/hardware.h>
 #include <linux/err.h>
+#include <time.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 struct chan_info {
@@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
 	u32 tmp, tmp1, tmp2;
 	u32 pwrup_srefresh_exit;
 	int ret;
+	const ulong timeout_ms = 200;
 
 	/*
 	 * work around controller bug:
@@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
 	clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 
 	/* Wating for PHY and DRAM init complete */
-	tmp = 0;
-	while (!(readl(&denali_ctl[203]) & (1 << 3))) {
-		mdelay(10);
-		tmp++;
-		if (tmp > 10)
+	tmp = get_timer(0);
+	do {
+		if (get_timer(tmp) > timeout_ms) {
+			error("DRAM (%s): phy failed to lock within  %ld ms\n",
+			      __func__, timeout_ms);
 			return -ETIME;
-	}
+		}
+	} while (!(readl(&denali_ctl[203]) & (1 << 3)));
+	debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 
 	clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 			pwrup_srefresh_exit);
-- 
1.9.1