[U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg registers
Calvin Johnson
calvin.johnson at nxp.com
Mon Oct 9 09:11:42 UTC 2017
Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg
registers of pfe.
Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 5c429d4..c6815f3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -577,6 +577,24 @@ int setup_chip_volt(void)
return 0;
}
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ out_be32(&scfg->pfeasbcr,
+ in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+ out_be32(&scfg->pfebsbcr,
+ in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+ /* CCI-400 QoS settings for PFE */
+ out_be32(&scfg->wr_qos1, 0x0ff00000);
+ out_be32(&scfg->rd_qos1, 0x0ff00000);
+
+ out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x524, 0x2000);
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 697f072..08a42b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -120,6 +120,9 @@ void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
/* Setup core vdd in unit mV */
int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
#endif
void ddr_enable_0v9_volt(bool en);
--
2.7.4
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