[U-Boot] [PATCH 3/3] x86: baytrail: fsp: Move Azalia update codes to board

[Bin Meng]

Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
---

 arch/x86/cpu/baytrail/fsp_configs.c                | 111 +--------------------
 .../som-db5800-som-6867/som-db5800-som-6867.c      | 111 +++++++++++++++++++++
 2 files changed, 113 insertions(+), 109 deletions(-)

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 3052fb6..6b762e5 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -12,122 +12,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* ALC262 Verb Table - 10EC0262 */
-static const u32 verb_table_data13[] = {
-	/* Pin Complex (NID 0x11) */
-	0x01171cf0,
-	0x01171d11,
-	0x01171e11,
-	0x01171f41,
-	/* Pin Complex (NID 0x12) */
-	0x01271cf0,
-	0x01271d11,
-	0x01271e11,
-	0x01271f41,
-	/* Pin Complex (NID 0x14) */
-	0x01471c10,
-	0x01471d40,
-	0x01471e01,
-	0x01471f01,
-	/* Pin Complex (NID 0x15) */
-	0x01571cf0,
-	0x01571d11,
-	0x01571e11,
-	0x01571f41,
-	/* Pin Complex (NID 0x16) */
-	0x01671cf0,
-	0x01671d11,
-	0x01671e11,
-	0x01671f41,
-	/* Pin Complex (NID 0x18) */
-	0x01871c20,
-	0x01871d98,
-	0x01871ea1,
-	0x01871f01,
-	/* Pin Complex (NID 0x19) */
-	0x01971c21,
-	0x01971d98,
-	0x01971ea1,
-	0x01971f02,
-	/* Pin Complex (NID 0x1A) */
-	0x01a71c2f,
-	0x01a71d30,
-	0x01a71e81,
-	0x01a71f01,
-	/* Pin Complex */
-	0x01b71c1f,
-	0x01b71d40,
-	0x01b71e21,
-	0x01b71f02,
-	/* Pin Complex */
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-	/* Pin Complex */
-	0x01d71c01,
-	0x01d71dc6,
-	0x01d71e14,
-	0x01d71f40,
-	/* Pin Complex */
-	0x01e71cf0,
-	0x01e71d11,
-	0x01e71e11,
-	0x01e71f41,
-	/* Pin Complex */
-	0x01f71cf0,
-	0x01f71d11,
-	0x01f71e11,
-	0x01f71f41,
-};
-
-/*
- * This needs to be in ROM since if we put it in CAR, FSP init loses it when
- * it drops CAR.
- *
- * TODO(sjg at chromium.org): Move to device tree when FSP allows it
- *
- * VerbTable: (RealTek ALC262)
- * Revision ID = 0xFF, support all steps
- * Codec Verb Table For AZALIA
- * Codec Address: CAd value (0/1/2)
- * Codec Vendor: 0x10EC0262
- */
-static const struct azalia_verb_table azalia_verb_table[] = {
-	{
-		{
-			0x10ec0262,
-			0x0000,
-			0xff,
-			0x01,
-			0x000b,
-			0x0002,
-		},
-		verb_table_data13
-	}
-};
-
-const struct azalia_config azalia_config = {
-	.pme_enable = 1,
-	.docking_supported = 1,
-	.docking_attached = 0,
-	.hdmi_codec_enable = 1,
-	.azalia_v_ci_enable = 1,
-	.rsvdbits = 0,
-	.verb_table_num = 1,
-	.verb_table = azalia_verb_table,
-	.reset_wait_timer_ms = 300
-};
-
 /**
  * Override the FSP's Azalia configuration data
  *
  * @azalia:	pointer to be updated to point to a ROM address where Azalia
  *		configuration data is stored
  */
-static void update_fsp_azalia_configs(struct azalia_config **azalia)
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
 {
-	*azalia = (struct azalia_config *)&azalia_config;
+	*azalia = NULL;
 }
 
 /**
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
index 6158795..202e9875 100644
--- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -6,6 +6,117 @@
  */
 
 #include <common.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const u32 verb_table_data13[] = {
+	/* Pin Complex (NID 0x11) */
+	0x01171cf0,
+	0x01171d11,
+	0x01171e11,
+	0x01171f41,
+	/* Pin Complex (NID 0x12) */
+	0x01271cf0,
+	0x01271d11,
+	0x01271e11,
+	0x01271f41,
+	/* Pin Complex (NID 0x14) */
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+	/* Pin Complex (NID 0x15) */
+	0x01571cf0,
+	0x01571d11,
+	0x01571e11,
+	0x01571f41,
+	/* Pin Complex (NID 0x16) */
+	0x01671cf0,
+	0x01671d11,
+	0x01671e11,
+	0x01671f41,
+	/* Pin Complex (NID 0x18) */
+	0x01871c20,
+	0x01871d98,
+	0x01871ea1,
+	0x01871f01,
+	/* Pin Complex (NID 0x19) */
+	0x01971c21,
+	0x01971d98,
+	0x01971ea1,
+	0x01971f02,
+	/* Pin Complex (NID 0x1A) */
+	0x01a71c2f,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+	/* Pin Complex */
+	0x01b71c1f,
+	0x01b71d40,
+	0x01b71e21,
+	0x01b71f02,
+	/* Pin Complex */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	/* Pin Complex */
+	0x01d71c01,
+	0x01d71dc6,
+	0x01d71e14,
+	0x01d71f40,
+	/* Pin Complex */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+	/* Pin Complex */
+	0x01f71cf0,
+	0x01f71d11,
+	0x01f71e11,
+	0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct azalia_verb_table azalia_verb_table[] = {
+	{
+		{
+			0x10ec0262,
+			0x0000,
+			0xff,
+			0x01,
+			0x000b,
+			0x0002,
+		},
+		verb_table_data13
+	}
+};
+
+static const struct azalia_config azalia_config = {
+	.pme_enable = 1,
+	.docking_supported = 1,
+	.docking_attached = 0,
+	.hdmi_codec_enable = 1,
+	.azalia_v_ci_enable = 1,
+	.rsvdbits = 0,
+	.verb_table_num = 1,
+	.verb_table = azalia_verb_table,
+	.reset_wait_timer_ms = 300
+};
+
+void update_fsp_azalia_configs(const struct azalia_config **azalia)
+{
+	*azalia = &azalia_config;
+}
 
 int board_early_init_f(void)
 {
-- 
2.7.4