[U-Boot] [PATCHv2] dm: pci: change bus number register setting compliant with Linux

[Zhiqiang Hou]

From: Minghuan Lian <Minghuan.Lian at nxp.com>

This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian at nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - Change uboot to U-Boot in commit message.

 drivers/pci/pci_auto.c        | 6 +++---
 drivers/pci/pcie_dw_mvebu.c   | 1 +
 drivers/pci/pcie_layerscape.c | 2 +-
 drivers/pci/pcie_xilinx.c     | 2 ++
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index ee9a854bda..c2bc32678a 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -181,8 +181,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 
 	/* Configure bus number registers */
 	dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
-			     PCI_BUS(dm_pci_get_bdf(dev)));
-	dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+			     PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
+	dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
 
 	if (pci_mem) {
@@ -257,7 +257,7 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
 	pci_io = ctlr_hose->pci_io;
 
 	/* Configure bus number registers */
-	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
 
 	if (pci_mem) {
 		/* Round memory allocator to 1MB boundary */
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 202cfe9d03..a19885501c 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -162,6 +162,7 @@ static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
 		/* Accessing root port configuration space. */
 		va_address = (uintptr_t)pcie->ctrl_base;
 	} else {
+		d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
 		writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
 		va_address = (uintptr_t)pcie->cfg_base;
 	}
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 610f85c4e8..48fc4efc75 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -250,7 +250,7 @@ void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
 	if (PCI_BUS(bdf) == bus->seq)
 		return pcie->dbi + offset;
 
-	busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
+	busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
 		 PCIE_ATU_DEV(PCI_DEV(bdf)) |
 		 PCIE_ATU_FUNC(PCI_FUNC(bdf));
 
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index 4ba32df516..72fc0f3c43 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -105,6 +105,7 @@ static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
 	void *address;
 	int err;
 
+	bdf = PCI_MASK_BUS(bdf) | (PCI_BUS(bdf) - bus->seq);
 	err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
 	if (err < 0) {
 		*valuep = pci_get_ff(size);
@@ -148,6 +149,7 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
 	void *address;
 	int err;
 
+	bdf = PCI_MASK_BUS(bdf) | (PCI_BUS(bdf) - bus->seq);
 	err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
 	if (err < 0)
 		return 0;
-- 
2.14.1