[U-Boot] [RFC] Attempt to Add SPL Support to imx6q_logic
Adam Ford
aford173 at gmail.com
Sat Oct 21 21:57:12 UTC 2017
The Logic PD i.MX6 dev kit is capable of SPL. This patch follows
a similar method as the mx6sabresd
Following instructions I found which show to put the SPL and .img
files on the SD card with dd.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
I would prefer to have the u-boot.img in a standard partition if
possible similar to how the omap3_logic board is done.
Unfortunately with DEBUG enabled in SPL, I only see:
U-Boot SPL 2017.11-rc2-00019-g23d51be-dirty (Oct 21 2017 - 16:14:59)
>>spl:board_init_r()
spl_early_init()
Trying to boot from MMC1
I was hoping someone with an i.MX6 might have some insight.
Signed-off-by: Adam Ford <aford173 at gmail.com>
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index b82db3a..750be47 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -189,6 +189,7 @@ config TARGET_MX6LOGICPD
select DM_PMIC
select DM_REGULATOR
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
index 1f3e378..4742ab8 100644
--- a/board/logicpd/imx6/imx6logic.c
+++ b/board/logicpd/imx6/imx6logic.c
@@ -61,6 +61,7 @@ static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+#ifndef CONFIG_SPL_BUILD
static void fixup_enet_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -109,6 +110,7 @@ static void fixup_enet_clock(void)
dm_gpio_set_value(&reset, 1);
mdelay(50);
}
+#endif
static void setup_iomux_uart(void)
{
@@ -159,7 +161,9 @@ int overwrite_console(void)
int board_early_init_f(void)
{
+#ifndef CONFIG_SPL_BUILD
fixup_enet_clock();
+#endif
setup_iomux_uart();
setup_nand_pins();
return 0;
@@ -183,3 +187,143 @@ int board_late_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <libfdt.h>
+#include <config.h>
+#include "asm/arch-mx6/mx6q-ddr.h"
+#include "asm/arch-mx6/iomux.h"
+#include "asm/arch-mx6/crm_regs.h"
+
+int spl_start_uboot(void)
+{
+ return 1;
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0xFFFFF300, &ccm->CCGR4);
+ writel(0x0F0000F3, &ccm->CCGR5);
+ writel(0x00000FFF, &ccm->CCGR6);
+}
+
+static int mx6q_dcd_table[] = {
+
+ MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+ MX6_IOM_GRP_DDRPKE, 0x00000000,
+ MX6_IOM_DRAM_SDCLK_0, 0x00000030,
+ MX6_IOM_DRAM_SDCLK_1, 0x00000030,
+ MX6_IOM_DRAM_CAS, 0x00000030,
+ MX6_IOM_DRAM_RAS, 0x00000030,
+ MX6_IOM_GRP_ADDDS, 0x00000030,
+ MX6_IOM_DRAM_RESET, 0x00000030,
+ MX6_IOM_DRAM_SDBA2, 0x00000000,
+ MX6_IOM_DRAM_SDODT0, 0x00000030,
+ MX6_IOM_DRAM_SDODT1, 0x00000030,
+ MX6_IOM_GRP_CTLDS, 0x00000030,
+ MX6_IOM_DDRMODE_CTL, 0x00020000,
+ MX6_IOM_DRAM_SDQS0, 0x00000030,
+ MX6_IOM_DRAM_SDQS1, 0x00000030,
+ MX6_IOM_DRAM_SDQS2, 0x00000030,
+ MX6_IOM_DRAM_SDQS3, 0x00000030,
+ MX6_IOM_GRP_DDRMODE, 0x00020000,
+ MX6_IOM_GRP_B0DS, 0x00000030,
+ MX6_IOM_GRP_B1DS, 0x00000030,
+ MX6_IOM_GRP_B2DS, 0x00000030,
+ MX6_IOM_GRP_B3DS, 0x00000030,
+ MX6_IOM_DRAM_DQM0, 0x00000030,
+ MX6_IOM_DRAM_DQM1, 0x00000030,
+ MX6_IOM_DRAM_DQM2, 0x00000030,
+ MX6_IOM_DRAM_DQM3, 0x00000030,
+ MX6_MMDC_P0_MDSCR, 0x00008000,
+ MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+ MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
+ MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
+ MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
+ MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
+ MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
+ MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
+ MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+ MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+ MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+ MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+ MX6_MMDC_P0_MPMUR0, 0x00000800,
+ MX6_MMDC_P0_MDPDC, 0x00020036,
+ MX6_MMDC_P0_MDOTC, 0x09444040,
+ MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
+ MX6_MMDC_P0_MDCFG1, 0xFF328F64,
+ MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+ MX6_MMDC_P0_MDMISC, 0x00011740,
+ MX6_MMDC_P0_MDSCR, 0x00008000,
+ MX6_MMDC_P0_MDRWD, 0x000026D2,
+ MX6_MMDC_P0_MDOR, 0x00BE1023,
+ MX6_MMDC_P0_MDASP, 0x00000047,
+ MX6_MMDC_P0_MDCTL, 0x85190000,
+ MX6_MMDC_P0_MDSCR, 0x00888032,
+ MX6_MMDC_P0_MDSCR, 0x00008033,
+ MX6_MMDC_P0_MDSCR, 0x00008031,
+ MX6_MMDC_P0_MDSCR, 0x19408030,
+ MX6_MMDC_P0_MDSCR, 0x04008040,
+ MX6_MMDC_P0_MDREF, 0x00007800,
+ MX6_MMDC_P0_MPODTCTRL, 0x00000007,
+ MX6_MMDC_P0_MDPDC, 0x00025576,
+ MX6_MMDC_P0_MAPSR, 0x00011006,
+ MX6_MMDC_P0_MDSCR, 0x00000000,
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ MX6_IOMUXC_GPR4, 0xF00000CF,
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ MX6_IOMUXC_GPR6, 0x007F007F,
+ MX6_IOMUXC_GPR7, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6dq())
+ ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* Setup UART and NAND */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
+
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 8018198..88e0de0 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -1,14 +1,27 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6LOGICPD=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="i.MX6 Logic # "
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -28,7 +41,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index c1e9f5d..6b37397 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -9,12 +9,26 @@
#ifndef __IMX6LOGIC_CONFIG_H
#define __IMX6LOGIC_CONFIG_H
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
#include <config_distro_defaults.h>
#include "mx6_common.h"
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+
+/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
--
2.7.4
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