[U-Boot] [PATCH v4 08/20] arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs

tien.fong.chee at intel.com tien.fong.chee at intel.com
Tue Oct 31 10:52:55 UTC 2017


From: Tien Fong Chee <tien.fong.chee at intel.com>

Add FPGA drivers to support FPGA loadfs to program FPGA.
The drivers are designed based on generic firmware loader framework,
specific firmware loader handling is defined in fpga_manager_arria10.c.
These drivers can handle FPGA program operation from
loading RBF image in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |   1 +
 arch/arm/mach-socfpga/fpga_manager_arria10.c       | 132 +++++++++
 .../include/mach/fpga_manager_arria10.h            |  32 ++
 drivers/fpga/socfpga_arria10.c                     | 330 +++++++++++++++++++++
 include/altera.h                                   |   6 +
 5 files changed, 501 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/fpga_manager_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..432a5a8 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -28,6 +28,7 @@ obj-y	+= clock_manager_arria10.o
 obj-y	+= misc_arria10.o
 obj-y	+= pinmux_arria10.o
 obj-y	+= reset_manager_arria10.o
+obj-$(CONFIG_CMD_FPGA_LOADFS) += fpga_manager_arria10.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/fpga_manager_arria10.c b/arch/arm/mach-socfpga/fpga_manager_arria10.c
new file mode 100644
index 0000000..42977aa
--- /dev/null
+++ b/arch/arm/mach-socfpga/fpga_manager_arria10.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <errno.h>
+#include <splash.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsloader_preprocess(struct splash_location *location, void *file_info,
+			char **filename, u32 bmp_load_addr)
+{
+	fpga_fs_info *fpga_fsinfo;
+	int len = 0;
+
+	fpga_fsinfo = (fpga_fs_info *)file_info;
+
+	fpga_fsinfo->dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+						       &len);
+
+	if (!fpga_fsinfo->dev_part) {
+		error("FPGA loadfs Error: Failed to get device partition.\n");
+		return -EPERM;
+	}
+
+	*filename = fpga_fsinfo->filename;
+
+	if (!*filename) {
+		error("FPGA loadfs Error: Failed to get filename.\n");
+		return -ENOENT;
+	}
+
+	if (fpga_fsinfo->interface) {
+		set_flash_devpart(fpga_fsinfo->interface,
+				  fpga_fsinfo->dev_part);
+	}
+
+	return 0;
+}
+
+int fs_loading(struct splash_location *location, void *file_info,
+	       char *filename, u32 bmp_load_addr, size_t bsize)
+{
+	struct flash_info flashinfo;
+	fpga_fs_info *fpga_fsinfo;
+	u32 status = 0;
+	int ret = 0;
+	u32 buffer = 0;
+	u32 buffer_ori = 0;
+	size_t buffer_sizebytes = 0;
+	size_t buffer_sizebytes_ori = 0;
+	buffer_sizebytes = buffer_sizebytes_ori = bsize;
+	buffer = buffer_ori = bmp_load_addr;
+
+	memset(&flashinfo, 0, sizeof(flashinfo));
+
+	fpga_fsinfo = (fpga_fs_info *)file_info;
+	flashinfo.interface = fpga_fsinfo->interface;
+	flashinfo.dev_part = fpga_fsinfo->dev_part;
+	flashinfo.filename = filename;
+	flashinfo.fstype = fpga_fsinfo->fstype;
+
+	WATCHDOG_RESET();
+	/*
+	 * Note: Both buffer and buffer_sizebytes values can be altered by
+	 * function below.
+	 */
+	ret = fs_flash_preinit(&flashinfo, &buffer, &buffer_sizebytes);
+
+	if (ret)
+		return ret;
+
+	if (flashinfo.rbfinfo.section == periph_section) {
+		/* Initialize the FPGA Manager */
+		status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
+		if (status) {
+			error("FPGA: Init with periph rbf failed with error.");
+			error("code %d\n", status);
+			return -EPERM;
+		}
+	}
+
+	WATCHDOG_RESET();
+
+	/* Transfer data to FPGA Manager */
+	fpgamgr_program_write((void *)buffer,
+		buffer_sizebytes);
+
+	WATCHDOG_RESET();
+
+	while (flashinfo.remaining) {
+		ret = fs_flash_read(&flashinfo, &buffer_ori,
+			&buffer_sizebytes_ori);
+
+		if (ret)
+			return ret;
+
+		/* Transfer data to FPGA Manager */
+		fpgamgr_program_write((void *)buffer_ori,
+			buffer_sizebytes_ori);
+
+		WATCHDOG_RESET();
+	}
+
+	if (flashinfo.rbfinfo.section == periph_section) {
+		if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT)
+			puts("FPGA: Early Release Succeeded.\n");
+		else {
+			puts("FPGA: Failed to see Early Release.\n");
+			return -EIO;
+		}
+	} else if (flashinfo.rbfinfo.section == core_section) {
+		/* Ensure the FPGA entering config done */
+		status = fpgamgr_program_finish();
+		if (status)
+			return status;
+		else
+			puts("FPGA: Enter user mode.\n");
+
+	} else {
+		puts("Config Error: Unsupported FGPA raw binary type.\n");
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..dc7337f 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -8,6 +8,8 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include <asm/cache.h>
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)
@@ -89,11 +91,41 @@ struct socfpga_fpga_manager {
 	u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+	enum rbf_type section;
+	enum rbf_security security;
+};
+
+struct flash_info {
+	char *interface;
+	char *dev_part;
+	char *filename;
+	int fstype;
+	u32 remaining;
+	u32 flash_offset;
+	struct rbf_info rbfinfo;
+	struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+int fs_flash_preinit(struct flash_info *flashinfo, u32 *buffer,
+		     u32 *buffer_sizebytes);
+int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,
+		  u32 *buffer_sizebytes);
+#endif
+void set_flash_devpart(char *name, char *devpart);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index e076bda..3f724ea 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -13,6 +13,13 @@
 #include <altera.h>
 #include <common.h>
 #include <errno.h>
+#include <fat.h>
+#include <fs.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <part.h>
+#include <splash.h>
+#include <spl.h>
 #include <wait_bit.h>
 #include <watchdog.h>
 
@@ -22,6 +29,10 @@
 #define COMPRESSION_OFFSET	229
 #define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT	0x1000000
+#define RBF_UNENCRYPTED		0xa65c
+#define RBF_ENCRYPTED		0xa65d
+#define ARRIA10RBF_PERIPH	0x0001
+#define ARRIA10RBF_CORE		0x8001
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,6 +44,32 @@ static const struct socfpga_system_manager *system_manager_base =
 
 static void fpgamgr_set_cd_ratio(unsigned long ratio);
 
+static struct splash_location default_flash_locations[] = {
+	{
+		.name = "mmc",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+};
+
+void set_flash_devpart(char *name, char *devpart)
+{
+	int i;
+	u32 size;
+
+	size = ARRAY_SIZE(default_flash_locations);
+
+	for (i = 0; i < size; i++) {
+		if (!strcmp(default_flash_locations[i].name, name))
+			default_flash_locations[i].devpart = devpart;
+		return;
+	}
+
+	error("No flash is found\n");
+	return;
+}
+
 static uint32_t fpgamgr_get_msel(void)
 {
 	u32 reg;
@@ -478,3 +515,296 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	return fpgamgr_program_finish();
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core)
+{
+	const char *cff_filename = NULL;
+	const char *cell;
+	int nodeoffset;
+	nodeoffset = fdtdec_next_compatible(fdt, 0,
+			 COMPAT_ALTERA_SOCFPGA_FPGA0);
+
+	if (nodeoffset >= 0) {
+		if (core)
+			cell = fdt_getprop(fdt,
+					nodeoffset,
+					"altr,bitstream_core",
+					len);
+		else
+			cell = fdt_getprop(fdt, nodeoffset,
+					"altr,bitstream_periph", len);
+
+		if (cell)
+			cff_filename = cell;
+	}
+
+	return cff_filename;
+}
+
+const char *get_cff_devpart(const void *fdt, int *len)
+{
+	const char *cff_devpart = NULL;
+	const char *cell;
+	int nodeoffset;
+	nodeoffset = fdtdec_next_compatible(fdt, 0,
+			 COMPAT_ALTERA_SOCFPGA_FPGA0);
+
+	cell = fdt_getprop(fdt, nodeoffset, "altr,bitstream_devpart", len);
+
+	if (cell)
+		cff_devpart = cell;
+
+	return cff_devpart;
+}
+
+void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
+{
+	/*
+	 * Magic ID starting at:
+	 * -> 1st dword in periph.rbf
+	 * -> 2nd dword in core.rbf
+	 */
+	u32 word_reading_max = 2;
+	u32 i;
+
+	for (i = 0; i < word_reading_max; i++) {
+		if (*(buffer + i) == RBF_UNENCRYPTED) /* PERIPH RBF */
+			rbf->security = unencrypted;
+		else if (*(buffer + i) == RBF_ENCRYPTED)
+			rbf->security = encrypted;
+		else if (*(buffer + i + 1) == RBF_UNENCRYPTED) /* CORE RBF */
+			rbf->security = unencrypted;
+		else if (*(buffer + i + 1) == RBF_ENCRYPTED)
+			rbf->security = encrypted;
+		else {
+			rbf->security = invalid;
+			continue;
+		}
+
+		/* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
+		if (*(buffer + i + 1) == ARRIA10RBF_PERIPH) {
+			rbf->section = periph_section;
+			break;
+		} else if (*(buffer + i + 1) == ARRIA10RBF_CORE) {
+			rbf->section = core_section;
+			break;
+		} else if (*(buffer + i + 2) == ARRIA10RBF_PERIPH) {
+			rbf->section = periph_section;
+			break;
+		} else if (*(buffer + i + 2) == ARRIA10RBF_CORE) {
+			rbf->section = core_section;
+			break;
+		} else {
+			rbf->section = unknown;
+			break;
+		}
+	}
+
+	return;
+}
+
+int flash_read(struct splash_location *location,
+	void *file_info,
+	size_t size_read,
+	u32 *buffer_ptr)
+{
+	size_t ret = EEXIST;
+	loff_t actread = 0;
+	struct flash_info *flashinfo = (struct flash_info *)file_info;
+
+	if (splash_select_fs_dev(location))
+		return FPGA_FAIL;
+
+	ret = fs_read(flashinfo->filename,
+			(u32) buffer_ptr, flashinfo->flash_offset,
+			size_read, &actread);
+
+	if (ret || actread != size_read) {
+		error("Failed to read %s from flash %d ",
+			flashinfo->filename,
+			 ret);
+		error("!= %d.\n", size_read);
+		return -EPERM;
+		} else
+			ret = actread;
+
+	return ret;
+}
+
+int fs_flash_preinit(struct flash_info *flashinfo,
+	u32 *buffer, u32 *buffer_sizebytes)
+{
+	u32 *bufferptr_after_header = NULL;
+	u32 buffersize_after_header = 0;
+	u32 rbf_header_data_size = 0;
+	int ret = 0;
+
+	flashinfo->flash_offset = 0;
+
+	/* To avoid from keeping re-read the contents */
+	struct image_header *header = &(flashinfo->header);
+	size_t buffer_size = *buffer_sizebytes;
+	u32 *buffer_ptr = (u32 *)*buffer;
+
+	 /* Load mkimage header into buffer */
+	ret = flash_read(default_flash_locations, flashinfo,
+			sizeof(struct image_header), buffer_ptr);
+
+	if (ret < 0) {
+		error(" Failed to read mkimage header from flash.\n");
+		return -ENOENT;
+	}
+
+	WATCHDOG_RESET();
+
+	memcpy(header, (u_char *)buffer_ptr, sizeof(*header));
+
+	if (!image_check_magic(header)) {
+		error("FPGA: Bad Magic Number.\n");
+		return -EBADF;
+	}
+
+	if (!image_check_hcrc(header)) {
+		error("FPGA: Bad Header Checksum.\n");
+		return -EPERM;
+	}
+
+	/* Getting rbf data size */
+	flashinfo->remaining =
+		image_get_data_size(header);
+
+	/* Calculate total size of both rbf data with mkimage header */
+	rbf_header_data_size = flashinfo->remaining +
+				sizeof(struct image_header);
+
+	/* Loading to buffer chunk by chunk, normally for OCRAM buffer */
+	if (rbf_header_data_size > buffer_size) {
+		/* Calculate size of rbf data in the buffer */
+		buffersize_after_header =
+			buffer_size - sizeof(struct image_header);
+		flashinfo->remaining -= buffersize_after_header;
+	} else {
+	/* Loading whole rbf image into buffer, normally for DDR buffer */
+		buffer_size = rbf_header_data_size;
+		/* Calculate size of rbf data in the buffer */
+		buffersize_after_header =
+			buffer_size - sizeof(struct image_header);
+		flashinfo->remaining = 0;
+	}
+
+	/* Loading mkimage header and rbf data into buffer */
+	ret = flash_read(default_flash_locations, flashinfo,
+				buffer_size, buffer_ptr);
+
+	if (ret < 0) {
+		error(" Failed to read mkimage header and rbf data ");
+		error("from flash.\n");
+		return -ENOENT;
+	}
+
+	/*
+	 * Getting pointer of rbf data starting address where is it
+	 * right after mkimage header
+	 */
+	bufferptr_after_header =
+		(u32 *)((u_char *)buffer_ptr + sizeof(struct image_header));
+
+	/* Update next reading rbf data flash offset */
+	flashinfo->flash_offset += buffer_size;
+
+	/*
+	 * Update the starting addr of rbf data to init FPGA & programming
+	 * into FPGA
+	 */
+	*buffer = (u32)bufferptr_after_header;
+
+	get_rbf_image_info(&flashinfo->rbfinfo, (u16 *)bufferptr_after_header);
+
+	/* Update the size of rbf data to be programmed into FPGA */
+	*buffer_sizebytes = buffersize_after_header;
+
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	flashinfo->datacrc =
+		crc32(flashinfo->datacrc,
+		(u_char *)bufferptr_after_header,
+		buffersize_after_header);
+#endif
+
+if (flashinfo->remaining == 0) {
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	if (flashinfo->datacrc !=
+		image_get_dcrc(&(flashinfo->header))) {
+		error("FPGA: Bad Data Checksum.\n");
+		return -EPERM;
+	}
+#endif
+}
+	return 0;
+}
+
+int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,
+	u32 *buffer_sizebytes)
+{
+	int ret = 0;
+	/* To avoid from keeping re-read the contents */
+	size_t buffer_size = *buffer_sizebytes;
+	u32 *buffer_ptr = (u32 *)*buffer;
+	u32 flash_addr = flashinfo->flash_offset;
+
+	/* Buffer allocated in OCRAM */
+	/* Read the data by small chunk by chunk. */
+	if (flashinfo->remaining > buffer_size)
+		flashinfo->remaining -= buffer_size;
+	else {
+		/*
+		 * Buffer allocated in DDR, larger than rbf data most
+		 * of the time
+		 */
+		buffer_size = flashinfo->remaining;
+		flashinfo->remaining = 0;
+	}
+
+	ret = flash_read(default_flash_locations, flashinfo,
+				buffer_size, buffer_ptr);
+
+	if (ret < 0) {
+		error(" Failed to read rbf data from flash.\n");
+		return -ENOENT;
+	}
+
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	flashinfo->datacrc =
+		crc32(flashinfo->datacrc,
+			(unsigned char *)buffer_ptr, buffer_size);
+#endif
+
+if (flashinfo->remaining == 0) {
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	if (flashinfo->datacrc !=
+		image_get_dcrc(&(flashinfo->header))) {
+		error("FPGA: Bad Data Checksum.\n");
+		return -EPERM;
+	}
+#endif
+}
+	/* Update next reading rbf data flash offset */
+	flash_addr += buffer_size;
+
+	flashinfo->flash_offset = flash_addr;
+
+	/* Update the size of rbf data to be programmed into FPGA */
+	*buffer_sizebytes = buffer_size;
+
+	return 0;
+}
+
+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo)
+{
+	WATCHDOG_RESET();
+
+	return splash_load_fs(default_flash_locations, fpga_fsinfo, (u32)buf,
+			      bsize);
+}
+#endif
diff --git a/include/altera.h b/include/altera.h
index 48d3eb7..0597e8a 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -84,6 +84,10 @@ typedef struct {
 extern int altera_load(Altera_desc *desc, const void *image, size_t size);
 extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
 extern int altera_info(Altera_desc *desc);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
+#endif
 
 /* Board specific implementation specific function types
  *********************************************************************/
@@ -111,6 +115,8 @@ typedef struct {
 
 #ifdef CONFIG_FPGA_SOCFPGA
 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
 #endif
 
 #ifdef CONFIG_FPGA_STRATIX_V
-- 
2.2.0



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