[U-Boot] [RFC 18/35] reset: sunxi: Add initial RESET driver for H3_H5

[Jagan Teki]

Add initial reset driver for Allwinner H3_H5.

Implement reset deassert and assert functions for
USB OHCI, EHCI, OTG and PHY bus reset and clock registers.

Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
 drivers/reset/sunxi/Kconfig    |   7 ++
 drivers/reset/sunxi/Makefile   |   1 +
 drivers/reset/sunxi/reset_h3.c | 121 +++++++++++++++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/reset/sunxi/reset_h3.c

diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig
index c0dfa56071..5c3b79eb76 100644
--- a/drivers/reset/sunxi/Kconfig
+++ b/drivers/reset/sunxi/Kconfig
@@ -9,6 +9,13 @@ config RESET_SUNXI
 
 if RESET_SUNXI
 
+config RESET_SUN8I_H3
+	bool "Reset driver for Allwinner H3/H5"
+	default MACH_SUNXI_H3_H5
+	help
+	  This enables common reset driver support for platforms based
+	  on Allwinner H3/H5 SoC.
+
 config RESET_SUN50I_A64
 	bool "Reset driver for Allwinner A64"
 	default MACH_SUN50I
diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile
index cc80b11818..6e4273b344 100644
--- a/drivers/reset/sunxi/Makefile
+++ b/drivers/reset/sunxi/Makefile
@@ -4,4 +4,5 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o
 obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o
diff --git a/drivers/reset/sunxi/reset_h3.c b/drivers/reset/sunxi/reset_h3.c
new file mode 100644
index 0000000000..e4794cadb9
--- /dev/null
+++ b/drivers/reset/sunxi/reset_h3.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan at amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+struct h3_reset_priv {
+	void *base;
+};
+
+static int h3_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(#%ld)\n", __func__, reset_ctl->id);
+
+	/* check dt-bindings/reset/sun8i-h3-ccu.h for max id */
+	if (reset_ctl->id > 54)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int h3_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(#%ld)\n", __func__, reset_ctl->id);
+
+	return 0;
+}
+
+static int h3_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct h3_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(#%ld)\n", __func__, reset_ctl->id);
+
+	switch (reset_ctl->id) {
+	case RST_USB_PHY0:
+	case RST_USB_PHY1:
+	case RST_USB_PHY2:
+	case RST_USB_PHY3:
+		clrbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id));
+		return 0;
+	case RST_BUS_OTG:
+	case RST_BUS_EHCI0:
+	case RST_BUS_EHCI1:
+	case RST_BUS_EHCI2:
+	case RST_BUS_EHCI3:
+	case RST_BUS_OHCI0:
+	case RST_BUS_OHCI1:
+	case RST_BUS_OHCI2:
+	case RST_BUS_OHCI3:
+		clrbits_le32(priv->base + 0x2c0,
+			     BIT(23 + (reset_ctl->id - RST_BUS_OTG)));
+		return 0;
+	default:
+		debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id);
+		return -ENODEV;
+	}
+}
+
+static int h3_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct h3_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(#%ld)\n", __func__, reset_ctl->id);
+
+	switch (reset_ctl->id) {
+	case RST_USB_PHY0:
+	case RST_USB_PHY1:
+	case RST_USB_PHY2:
+	case RST_USB_PHY3:
+		setbits_le32(priv->base + 0x0cc, BIT(reset_ctl->id));
+		return 0;
+	case RST_BUS_OTG:
+	case RST_BUS_EHCI0:
+	case RST_BUS_EHCI1:
+	case RST_BUS_EHCI2:
+	case RST_BUS_EHCI3:
+	case RST_BUS_OHCI0:
+	case RST_BUS_OHCI1:
+	case RST_BUS_OHCI2:
+	case RST_BUS_OHCI3:
+		setbits_le32(priv->base + 0x2c0,
+			     BIT(23 + (reset_ctl->id - RST_BUS_OTG)));
+		return 0;
+	default:
+		debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id);
+		return -ENODEV;
+	}
+}
+
+struct reset_ops h3_reset_ops = {
+	.request = h3_reset_request,
+	.free = h3_reset_free,
+	.rst_assert = h3_reset_assert,
+	.rst_deassert = h3_reset_deassert,
+};
+
+static int h3_reset_probe(struct udevice *dev)
+{
+	struct h3_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(reset_sun8i_h3) = {
+	.name		= "sun8i_h3_reset",
+	.id		= UCLASS_RESET,
+	.ops		= &h3_reset_ops,
+	.probe		= h3_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct h3_reset_priv),
+};
-- 
2.17.1