[U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL
Michal Simek
michal.simek at xilinx.com
Wed Jul 18 08:00:12 UTC 2018
On 18.7.2018 09:41, Luis Araneda wrote:
> This series implements FPGA bitstream loading from SPL.
> Programming the FPGA from the SPL is necessary on some boards,
> like the Zybo, because the FPGA fabric routes the I2C bus to an
> EEPROM for reading the Ethernet MAC address.
>
> The bitstream is loaded from a FIT image into a dynamically-allocated
> memory before programming the FPGA.
>
> Additionally, some fixes are applied to compile the zynqpl driver
> for SPL, and to properly detect an FPGA from the SPL.
>
> I'm not sure if the fixes are correct or I'm missing something,
> hence the RFC.
>
> Tested on a Digilent Zybo Z7-20 board
>
> Luis Araneda (4):
> spl: fit: display a message when an FPGA image is loaded
> drivers: fpga: zynqpl: fix compilation with SPL
> arm: zynq: spl: fix FPGA initialization
> arm: zynq: spl: implement FPGA load from FIT
>
> arch/arm/mach-zynq/spl.c | 42 ++++++++++++++++++++++++++++++++++++++++
> common/spl/spl_fit.c | 1 +
> drivers/fpga/zynqpl.c | 4 ++--
> 3 files changed, 45 insertions(+), 2 deletions(-)
>
Can you please also send defconfig/config changes?
Separate patch is fine.
Thanks,
Michal
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