[U-Boot] [PATCH v2 09/11] net: phy: ti: Add binding for the CLK_OUT pin muxing

[Janine Hagemann]

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann at phytec.de>
---
v2: - Change commit reference format
    - Add a/doc/device-tree-bindings/net/ti,dp83867.txt
    - Use GENMASK() for shift
    - Correct multi-line comment format
---
 doc/device-tree-bindings/net/ti,dp83867.txt |  3 +++
 drivers/net/phy/ti.c                        | 25 +++++++++++++++++++++++++
 include/dt-bindings/net/ti-dp83867.h        | 15 +++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
index cb77fdf..2561caa 100644
--- a/doc/device-tree-bindings/net/ti,dp83867.txt
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -8,6 +8,8 @@ Required properties:
 		for applicable values
 	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
 		for applicable values
+	- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
+		for applicable values
 
 Default child nodes are standard Ethernet PHY device
 nodes as described in doc/devicetree/bindings/net/ethernet.txt
@@ -19,6 +21,7 @@ Example:
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 	};
 
 Datasheet can be found:
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index f0ca8f2..a509aed 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -95,6 +95,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
 
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)
@@ -112,6 +114,7 @@ struct dp83867_private {
 	int io_impedance;
 	int port_mirroring;
 	bool rxctrl_strap_quirk;
+	int clk_output_sel;
 };
 
 /**
@@ -212,6 +215,17 @@ static int dp83867_of_init(struct phy_device *phydev)
 	struct udevice *dev = phydev->dev;
 	int node = dev_of_offset(dev);
 	const void *fdt = gd->fdt_blob;
+	u16 val;
+
+	/* Optional configuration */
+
+	/*
+	 * Keep the default value if ti,clk-output-sel is not set
+	 * or to high
+	 */
+
+	dp83867->clk_output_sel = fdtdec_get_uint(fdt, node,
+						  "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
 
 	if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
@@ -238,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev)
 	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 				 "ti,fifo-depth", -1);
 
+	/* Clock output selection if muxing property is set */
+	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+		val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+					    DP83867_DEVADDR, phydev->addr);
+		val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+		val |= (dp83867->clk_output_sel <<
+			DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+		phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+					DP83867_DEVADDR, phydev->addr, val);
+	}
+
 	return 0;
 }
 #else
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index b8e5df6..85d08f6 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -31,4 +31,19 @@
 #define DP83867_RGMIIDCTL_3_75_NS	0xe
 #define DP83867_RGMIIDCTL_4_00_NS	0xf
 
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK		0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK		0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK		0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK		0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK		0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK		0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
+#define DP83867_CLK_O_SEL_REF_CLK		0xC
+
 #endif
-- 
2.7.4