[U-Boot] [PATCH] spl: fpga: Implement fpga bistream loading with fpga_load

[Marek Vasut]

On 07/18/2018 02:51 PM, Michal Simek wrote:
> There shouldn't be a need to call private spl_load_fpga_image()
> because the whole sequence should be already handled by fpga_load().
> The patch let spl_load_fit_image() to load data to right location based
> on "load" property in FIT and then call fpga_load().

NAK

This breaks Arria10, sorry. The private loading function is needed on
Arria10 as the whole bitstream is not available in RAM and needs to be
loaded piece by piece, see [1]

[1]
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=blobdiff;f=arch/arm/mach-socfpga/spl.c;h=82adb5dfb8de62e3d928f6f4405705f3f32a780c;hp=7ee988a2d59831ec6bff927b2a5fdad7f57da055;hb=21f835ebf2b40fc8a3e8b818c5c5ba2555dd7c65;hpb=bd198801cb95b5a8460c95a762cc4a9a44ca85ef

> The patch is partially reverting
> "spl: fit: Add support for loading FPGA bitstream"
> (sha1: 26a642238bdecc53527142dc043b29e21c5cc94c)
> 
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
> 
> <debug_uart> Debug uart enabled
> 
> U-Boot SPL 2018.07-00185-g4c2b86d7a763 (Jul 18 2018 - 14:49:35 +0200)
> mmc boot
> Trying to boot from MMC1
> spl_load_image_fat_os: error reading image system.dtb, err - -2
> zynq_align_dma_buffer: Bitstream is not swapped(1) - swap it
> FPGA image loaded from FIT
> 
> U-Boot 2018.07-00185-g4c2b86d7a763 (Jul 18 2018 - 14:49:35 +0200) Xilinx
> Zynq ZC706
> 
> CPU:   Zynq 7z045
> Silicon: v1.0
> Model: Zynq ZC706 Development Board
> I2C:   ready
> DRAM:  ECC disabled 1 GiB
> Watchdog: Started
> MMC:   sdhci at e0100000: 0
> Loading Environment from SPI Flash... SF: Detected s25fl128s_64k with
> page size 256 Bytes, erase size 64 KiB, total 16 MiB
> *** Warning - bad CRC, using default environment
> 
> Failed (-5)
> In:    serial at e0001000
> Out:   serial at e0001000
> Err:   serial at e0001000
> Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
> 
> Warning: ethernet at e000b000 (eth0) using random MAC address -
> 6e:3a:1c:22:aa:5f
> eth0: ethernet at e000b000
> Checking if uenvcmd is set ...
> Hit any key to stop autoboot:  0
> Zynq>
> 
> ---
>  common/spl/spl_fit.c | 34 ++++++++++++++++------------------
>  1 file changed, 16 insertions(+), 18 deletions(-)
> 
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index 9eabb1c1058b..8ab6a2def1e2 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -6,6 +6,7 @@
>  
>  #include <common.h>
>  #include <errno.h>
> +#include <fpga.h>
>  #include <image.h>
>  #include <linux/libfdt.h>
>  #include <spl.h>
> @@ -140,14 +141,6 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size,
>  	return (data_size + info->bl_len - 1) / info->bl_len;
>  }
>  
> -#ifdef CONFIG_SPL_FPGA_SUPPORT
> -__weak int spl_load_fpga_image(struct spl_load_info *info, size_t length,
> -			       int nr_sectors, int sector_offset)
> -{
> -	return 0;
> -}
> -#endif
> -
>  /**
>   * spl_load_fit_image(): load the image described in a certain FIT node
>   * @info:	points to information about the device to load data from
> @@ -169,7 +162,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
>  			      void *fit, ulong base_offset, int node,
>  			      struct spl_image_info *image_info)
>  {
> -	int offset, sector_offset;
> +	int offset;
>  	size_t length;
>  	int len;
>  	ulong size;
> @@ -217,16 +210,9 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
>  
>  		overhead = get_aligned_image_overhead(info, offset);
>  		nr_sectors = get_aligned_image_size(info, length, offset);
> -		sector_offset = sector + get_aligned_image_offset(info, offset);
> -
> -#ifdef CONFIG_SPL_FPGA_SUPPORT
> -		if (type == IH_TYPE_FPGA) {
> -			return spl_load_fpga_image(info, length, nr_sectors,
> -						   sector_offset);
> -		}
> -#endif
>  
> -		if (info->read(info, sector_offset,
> +		if (info->read(info,
> +			       sector + get_aligned_image_offset(info, offset),
>  			       nr_sectors, (void *)load_ptr) != nr_sectors)
>  			return -EIO;
>  
> @@ -412,6 +398,18 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
>  			printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
>  			return ret;
>  		}
> +
> +		debug("FPGA bitstream at: %x, size: %x\n",
> +		      (u32)spl_image->load_addr, spl_image->size);
> +
> +		ret = fpga_load(0, (const void *)spl_image->load_addr,
> +				spl_image->size, BIT_FULL);
> +		if (ret) {
> +			printf("%s: Cannot load the image to the FPGA\n",
> +			       __func__);
> +			return ret;
> +		}
> +
>  		puts("FPGA image loaded from FIT\n");
>  		node = -1;
>  	}
> 


-- 
Best regards,
Marek Vasut