[U-Boot] [PATCH v2 5/5] x86: Switch to use DM sysreset driver
Bin Meng
bmeng.cn at gmail.com
Thu Jul 19 10:07:33 UTC 2018
This converts all x86 boards over to DM sysreset.
Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
---
Changes in v2:
- remove include of "reset.dsti" in edison.dts
- add SYSRESET for efi-x86_app and edison
arch/Kconfig | 2 ++
arch/x86/cpu/baytrail/valleyview.c | 6 ------
arch/x86/cpu/braswell/braswell.c | 6 ------
arch/x86/cpu/cpu.c | 26 --------------------------
arch/x86/cpu/ivybridge/early_me.c | 7 ++++---
arch/x86/cpu/ivybridge/sdram.c | 3 ++-
arch/x86/cpu/qemu/qemu.c | 6 ------
arch/x86/cpu/quark/quark.c | 6 ------
arch/x86/cpu/tangier/tangier.c | 6 ------
arch/x86/dts/bayleybay.dts | 1 +
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 1 +
arch/x86/dts/broadwell_som-6896.dts | 1 +
arch/x86/dts/cherryhill.dts | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/chromebook_samus.dts | 1 +
arch/x86/dts/chromebox_panther.dts | 1 +
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 1 +
arch/x86/dts/cougarcanyon2.dts | 1 +
arch/x86/dts/crownbay.dts | 1 +
arch/x86/dts/dfi-bt700.dtsi | 1 +
arch/x86/dts/edison.dts | 5 +++++
arch/x86/dts/efi-x86_app.dts | 5 +++++
arch/x86/dts/efi-x86_payload.dts | 1 +
arch/x86/dts/galileo.dts | 1 +
arch/x86/dts/minnowmax.dts | 1 +
arch/x86/dts/qemu-x86_i440fx.dts | 1 +
arch/x86/dts/qemu-x86_q35.dts | 1 +
arch/x86/dts/reset.dtsi | 6 ++++++
arch/x86/include/asm/processor.h | 5 -----
arch/x86/include/asm/u-boot-x86.h | 1 -
configs/chromebook_link64_defconfig | 1 +
31 files changed, 41 insertions(+), 66 deletions(-)
create mode 100644 arch/x86/dts/reset.dtsi
diff --git a/arch/Kconfig b/arch/Kconfig
index dd5a887..cbeb9f6 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -118,6 +118,8 @@ config X86
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
+ imply SYSRESET
+ imply SYSRESET_X86
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index b7d481a..8882a76 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -55,9 +55,3 @@ int arch_misc_init(void)
return 0;
}
-
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- x86_full_reset();
-}
diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
index 32a6a5e..7a83b06 100644
--- a/arch/x86/cpu/braswell/braswell.c
+++ b/arch/x86/cpu/braswell/braswell.c
@@ -27,9 +27,3 @@ int arch_misc_init(void)
return 0;
}
-
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- x86_full_reset();
-}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 99f8e68..290ee08 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -76,37 +76,11 @@ int x86_init_cache(void)
}
int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("resetting ...\n");
-
- /* wait 50 ms */
- udelay(50000);
- disable_interrupts();
- reset_cpu(0);
-
- /*NOTREACHED*/
- return 0;
-}
-
void flush_cache(unsigned long dummy1, unsigned long dummy2)
{
asm("wbinvd\n");
}
-__weak void reset_cpu(ulong addr)
-{
- /* Do a hard reset through the chipset's reset control register */
- outb(SYS_RST | RST_CPU, IO_PORT_RESET);
- for (;;)
- cpu_hlt();
-}
-
-void x86_full_reset(void)
-{
- outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
-}
-
/* Define these functions to allow ehch-hcd to function */
void flush_dcache_range(unsigned long start, unsigned long stop)
{
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index 1a15229..219d5be 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <sysreset.h>
#include <asm/pci.h>
#include <asm/cpu.h>
#include <asm/processor.h>
@@ -138,17 +139,17 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(dev, 0);
- reset_cpu(0);
+ sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(dev, 0);
- x86_full_reset();
+ sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(dev, 1);
- x86_full_reset();
+ sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 2f253e8..8a58d03 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -18,6 +18,7 @@
#include <spi.h>
#include <spi_flash.h>
#include <syscon.h>
+#include <sysreset.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/gpio.h>
@@ -497,7 +498,7 @@ int dram_init(void)
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
debug("Giving up in sdram_initialize: No MRC data\n");
- reset_cpu(0);
+ sysreset_walk_halt(SYSRESET_COLD);
}
/* Pass console handler in pei_data */
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index ca4b3f0..5e8b4f0 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -156,12 +156,6 @@ int print_cpuinfo(void)
}
#endif
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- x86_full_reset();
-}
-
int arch_early_init_r(void)
{
qemu_chipset_init();
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 4fd6864..d39edb2 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -270,12 +270,6 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- x86_full_reset();
-}
-
static void quark_pcie_init(void)
{
u32 val;
diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c
index 0a15e64..df2c600 100644
--- a/arch/x86/cpu/tangier/tangier.c
+++ b/arch/x86/cpu/tangier/tangier.c
@@ -4,7 +4,6 @@
*/
#include <common.h>
-#include <asm/scu.h>
#include <asm/u-boot-x86.h>
/*
@@ -24,8 +23,3 @@ int print_cpuinfo(void)
{
return default_print_cpuinfo();
}
-
-void reset_cpu(ulong addr)
-{
- scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
-}
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 74291a8..9683c52 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 36e6069..4e8a761 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 3966199..ec691f1 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -2,6 +2,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 3e29683..39e2d2f 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 26b9f85..115a088 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -5,6 +5,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 52a9ea6..9c48c9a 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -5,6 +5,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index b25c919..a72a85e 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -2,6 +2,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index c3d1514..5884dbc 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index c1cda73..9801790 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d8faa9d..2ffcc5f 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index cb96fdf..51d33e7 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-router/intel-irq.h>
#include "skeleton.dtsi"
+#include "reset.dtsi"
#include "rtc.dtsi"
#include "tsc_timer.dtsi"
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index 9033532..5c80f5c 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -85,4 +85,9 @@
compatible = "intel,scu-ipc";
reg = <0xff009000 0x1000>;
};
+
+ reset {
+ compatible = "intel,reset-tangier";
+ u-boot,dm-pre-reloc;
+ };
};
diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts
index e70e351..20150f6 100644
--- a/arch/x86/dts/efi-x86_app.dts
+++ b/arch/x86/dts/efi-x86_app.dts
@@ -23,4 +23,9 @@
serial: serial {
compatible = "efi,uart";
};
+
+ reset {
+ compatible = "efi,reset";
+ u-boot,dm-pre-reloc;
+ };
};
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 148b587..19f2530 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 3454abd..3a5d168 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 42ba0c7..02ab4c1 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 6565429..2e5210d 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index f1c4cb9..e8f55b1 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -20,6 +20,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi
new file mode 100644
index 0000000..f979d83
--- /dev/null
+++ b/arch/x86/dts/reset.dtsi
@@ -0,0 +1,6 @@
+/ {
+ reset {
+ compatible = "x86,reset";
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index dd957d2..f1d9977 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -43,11 +43,6 @@ enum {
FULL_RST = 1 << 3, /* full power cycle */
};
-/**
- * x86_full_reset() - reset everything: perform a full power cycle
- */
-void x86_full_reset(void);
-
static inline __attribute__((always_inline)) void cpu_hlt(void)
{
asm("hlt");
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 2340ef8..670fcdc 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -40,7 +40,6 @@ int x86_cleanup_before_linux(void);
void x86_enable_caches(void);
void x86_disable_caches(void);
int x86_init_cache(void);
-void reset_cpu(ulong addr);
ulong board_get_usable_ram_top(ulong total_size);
int default_print_cpuinfo(void);
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 59b6bd0..9af2c4d 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
--
2.7.4
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