[U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL

[Luis Araneda]

Hi Michal,

On Fri, Jul 20, 2018 at 6:38 AM Michal Simek <michal.simek at xilinx.com> wrote:
> On 20.7.2018 01:37, Luis Araneda wrote:
> > Hi Michal,
> >
> > On Thu, Jul 19, 2018 at 2:23 AM Michal Simek <michal.simek at xilinx.com> wrote:
> We need that functionality first but then enable it for all boards is
> fine for me and via one patch.

Ok

> Can you please be more specific what time1/time2 and time3 means?

The exact location of time 1/2/3 are on the attached diff file, and
they are placed within the spl_load_simple_fit() function.
They represent, roughly:
- time1: Time to load the the FIT image
- time2: Time to extract (and decompress)
  the FPGA image from the FIT image
- time3: Time to program the FPGA

Thanks,

Luis Araneda.