[U-Boot] [PATCH 1/1] arm: socfpga: Add support for the ReflexCES R329 board
Xavier Ruppen
xruppen at gmail.com
Tue Jul 24 17:21:57 UTC 2018
The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides
access to all the features of the Arria 10 SoC SoM (R315) (Ethernet,
OTG USB, Transceivers, UART) and adds further functions, including SFP+
connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.
No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on
this board. Thus, a bitstream is loaded before booting by using the EPCQ.
It is possible to load a bitstream from the HPS (packaged in the .sfp file)
but a small hardware mod on the MSEL lines is required (tested and works).
Signed-off-by: Xavier Ruppen <xruppen at gmail.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Chin Liang See <chin.liang.see at intel.com>
Cc: Dinh Nguyen <dinguyen at kernel.org>
---
This patch was created and tested against u-boot-socfpga/arria10_sdmmc.
The handoff.dtsi file was created by meld'ing the (old) .dts file provided
by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.
The board was tested with what I believe is the factory bitstream written
in the EPCQ.
As I copied and pasted the majority of the files from the arria10-socdk,
I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines
and a missing SPDX-License-Identifier in the .dts(i) files.
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10_r329.dts | 108 ++++++
.../arm/dts/socfpga_arria10_r329_handoff.dtsi | 350 ++++++++++++++++++
arch/arm/mach-socfpga/Kconfig | 7 +
board/reflexces/r329-a10-pcie/Kconfig | 18 +
board/reflexces/r329-a10-pcie/MAINTAINERS | 8 +
board/reflexces/r329-a10-pcie/Makefile | 5 +
.../reflexces/r329-a10-pcie/fit_spl_fpga.its | 45 +++
board/reflexces/r329-a10-pcie/socfpga.c | 6 +
configs/socfpga_r329_a10_pcie_defconfig | 67 ++++
include/configs/socfpga_r329_a10_pcie.h | 50 +++
11 files changed, 665 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_r329.dts
create mode 100644 arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
create mode 100644 board/reflexces/r329-a10-pcie/Kconfig
create mode 100644 board/reflexces/r329-a10-pcie/MAINTAINERS
create mode 100644 board/reflexces/r329-a10-pcie/Makefile
create mode 100644 board/reflexces/r329-a10-pcie/fit_spl_fpga.its
create mode 100644 board/reflexces/r329-a10-pcie/socfpga.c
create mode 100644 configs/socfpga_r329_a10_pcie_defconfig
create mode 100644 include/configs/socfpga_r329_a10_pcie.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 946023093d..05cd7af467 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -188,6 +188,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
+ socfpga_arria10_r329.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_r329.dts b/arch/arm/dts/socfpga_arria10_r329.dts
new file mode 100644
index 0000000000..8869ef0fe7
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_r329.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_r329_handoff.dtsi"
+
+/ {
+ model = "Reflex CES R329 SOM-A10 PCIe";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0xC0000000>; /* 3GB */
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+
+ /*
+ * These skews assume the user's FPGA design is adding 600ps of delay
+ * for TX_CLK on Arria 10.
+ *
+ * All skews are offset since hardware skew values for the ksz9031
+ * range from a negative skew to a positive skew.
+ * See the micrel-ksz90x1.txt Documentation file for details.
+ */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+ status = "okay";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ num-slots = <1>;
+ cap-sd-highspeed;
+ bus-width = <4>;
+ non-removable;
+};
+
+&eccmgr {
+ sdmmca-ecc at ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi b/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
new file mode 100644
index 0000000000..462cad912c
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ *<auto-generated>
+ * This code was generated by a tool based on
+ * handoffs from both Qsys and Quartus.
+ *
+ * Changes to this file may be lost if
+ * the code is regenerated.
+ *</auto-generated>
+ */
+
+#include "socfpga_arria10.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
+
+ chosen {
+ cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
+ };
+
+ /* Clock sources */
+ clocks {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Clock source: altera_arria10_hps_eosc1 */
+ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "altera_arria10_hps_eosc1-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_cb_intosc_ls */
+ altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_f2h_free */
+ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "altera_arria10_hps_f2h_free-clk";
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_clk_mgr: clock_manager at 0xffd04000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-clk-init";
+ reg = <0xffd04000 0x00000200>;
+ reg-names = "soc_clock_manager_OCP_SLV";
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
+ mainpll {
+ u-boot,dm-pre-reloc;
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <127>; /* Field: vco1.numer */
+ mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
+ mpuclk-src = <0>; /* Field: mpuclk.src */
+ nocclk-cnt = <0>; /* Field: nocclk.cnt */
+ nocclk-src = <0>; /* Field: nocclk.src */
+ cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
+ cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
+ cntr6clk-cnt = <7>; /* Field: cntr6clk.cnt */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr7clk-src = <0>; /* Field: cntr7clk.src */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ cntr9clk-src = <0>; /* Field: cntr9clk.src */
+ cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
+ nocdiv-l4mainclk = <2>; /* Field: nocdiv.l4mainclk */
+ nocdiv-l4mpclk = <2>; /* Field: nocdiv.l4mpclk */
+ nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
+ nocdiv-csatclk = <2>; /* Field: nocdiv.csatclk */
+ nocdiv-cstraceclk = <0>; /* Field: nocdiv.cstraceclk */
+ nocdiv-cspdbgclk = <0>; /* Field: nocdiv.cspdbgclk */
+ };
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
+ perpll {
+ u-boot,dm-pre-reloc;
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <119>; /* Field: vco1.numer */
+ cntr2clk-cnt = <5>; /* Field: cntr2clk.cnt */
+ cntr2clk-src = <1>; /* Field: cntr2clk.src */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr3clk-src = <1>; /* Field: cntr3clk.src */
+ cntr4clk-cnt = <14>; /* Field: cntr4clk.cnt */
+ cntr4clk-src = <1>; /* Field: cntr4clk.src */
+ cntr5clk-cnt = <374>; /* Field: cntr5clk.cnt */
+ cntr5clk-src = <1>; /* Field: cntr5clk.src */
+ cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
+ cntr6clk-src = <0>; /* Field: cntr6clk.src */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr8clk-src = <0>; /* Field: cntr8clk.src */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
+ emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
+ emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
+ gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
+ };
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ nocclk = <0x03840003>; /* Register: nocclk */
+ mpuclk = <0x03840001>; /* Register: mpuclk */
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: pinmux
+ */
+ i_io48_pin_mux: pinmux at 0xffd07000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "pinctrl-single";
+ reg = <0xffd07000 0x00000800>;
+ reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
+ shared {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07000 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x00000000 0x0000000d>, /* Register: pinmux_shared_io_q1_1 */
+ <0x00000004 0x0000000d>, /* Register: pinmux_shared_io_q1_2 */
+ <0x00000008 0x0000000d>, /* Register: pinmux_shared_io_q1_3 */
+ <0x0000000c 0x0000000d>, /* Register: pinmux_shared_io_q1_4 */
+ <0x00000010 0x00000000>, /* Register: pinmux_shared_io_q1_5 */
+ <0x00000014 0x00000000>, /* Register: pinmux_shared_io_q1_6 */
+ <0x00000018 0x00000001>, /* Register: pinmux_shared_io_q1_7 */
+ <0x0000001c 0x00000001>, /* Register: pinmux_shared_io_q1_8 */
+ <0x00000020 0x00000001>, /* Register: pinmux_shared_io_q1_9 */
+ <0x00000024 0x00000001>, /* Register: pinmux_shared_io_q1_10 */
+ <0x00000028 0x0000000a>, /* Register: pinmux_shared_io_q1_11 */
+ <0x0000002c 0x0000000a>, /* Register: pinmux_shared_io_q1_12 */
+ <0x00000030 0x00000008>, /* Register: pinmux_shared_io_q2_1 */
+ <0x00000034 0x00000008>, /* Register: pinmux_shared_io_q2_2 */
+ <0x00000038 0x00000008>, /* Register: pinmux_shared_io_q2_3 */
+ <0x0000003c 0x00000008>, /* Register: pinmux_shared_io_q2_4 */
+ <0x00000040 0x00000008>, /* Register: pinmux_shared_io_q2_5 */
+ <0x00000044 0x00000008>, /* Register: pinmux_shared_io_q2_6 */
+ <0x00000048 0x00000008>, /* Register: pinmux_shared_io_q2_7 */
+ <0x0000004c 0x00000008>, /* Register: pinmux_shared_io_q2_8 */
+ <0x00000050 0x00000008>, /* Register: pinmux_shared_io_q2_9 */
+ <0x00000054 0x00000008>, /* Register: pinmux_shared_io_q2_10 */
+ <0x00000058 0x00000008>, /* Register: pinmux_shared_io_q2_11 */
+ <0x0000005c 0x00000008>, /* Register: pinmux_shared_io_q2_12 */
+ <0x00000060 0x00000008>, /* Register: pinmux_shared_io_q3_1 */
+ <0x00000064 0x00000008>, /* Register: pinmux_shared_io_q3_2 */
+ <0x00000068 0x00000008>, /* Register: pinmux_shared_io_q3_3 */
+ <0x0000006c 0x00000008>, /* Register: pinmux_shared_io_q3_4 */
+ <0x00000070 0x00000008>, /* Register: pinmux_shared_io_q3_5 */
+ <0x00000074 0x00000008>, /* Register: pinmux_shared_io_q3_6 */
+ <0x00000078 0x00000008>, /* Register: pinmux_shared_io_q3_7 */
+ <0x0000007c 0x00000008>, /* Register: pinmux_shared_io_q3_8 */
+ <0x00000080 0x00000008>, /* Register: pinmux_shared_io_q3_9 */
+ <0x00000084 0x00000008>, /* Register: pinmux_shared_io_q3_10 */
+ <0x00000088 0x00000008>, /* Register: pinmux_shared_io_q3_11 */
+ <0x0000008c 0x00000008>, /* Register: pinmux_shared_io_q3_12 */
+ <0x00000090 0x00000008>, /* Register: pinmux_shared_io_q4_1 */
+ <0x00000094 0x00000008>, /* Register: pinmux_shared_io_q4_2 */
+ <0x00000098 0x00000008>, /* Register: pinmux_shared_io_q4_3 */
+ <0x0000009c 0x00000008>, /* Register: pinmux_shared_io_q4_4 */
+ <0x000000a0 0x00000008>, /* Register: pinmux_shared_io_q4_5 */
+ <0x000000a4 0x00000008>, /* Register: pinmux_shared_io_q4_6 */
+ <0x000000a8 0x00000008>, /* Register: pinmux_shared_io_q4_7 */
+ <0x000000ac 0x00000008>, /* Register: pinmux_shared_io_q4_8 */
+ <0x000000b0 0x00000008>, /* Register: pinmux_shared_io_q4_9 */
+ <0x000000b4 0x00000008>, /* Register: pinmux_shared_io_q4_10 */
+ <0x000000b8 0x00000008>, /* Register: pinmux_shared_io_q4_11 */
+ <0x000000bc 0x00000008>; /* Register: pinmux_shared_io_q4_12 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
+ <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
+ <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
+ <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
+ <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
+ <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
+ <0x0000003c 0x0000000f>, /* Register: pinmux_dedicated_io_16 */
+ <0x00000040 0x0000000f>; /* Register: pinmux_dedicated_io_17 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x003f3f3f>;
+ pinctrl-single,pins =
+ <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
+ <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
+ <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
+ <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
+ <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
+ <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
+ <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
+ <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
+ <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
+ <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
+ <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
+ <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
+ <0x00000130 0x000a282a>, /* Register: configuration_dedicated_io_12 */
+ <0x00000134 0x000a282a>, /* Register: configuration_dedicated_io_13 */
+ <0x00000138 0x000a282a>, /* Register: configuration_dedicated_io_14 */
+ <0x0000013c 0x000a282a>, /* Register: configuration_dedicated_io_15 */
+ <0x00000140 0x000a282a>, /* Register: configuration_dedicated_io_16 */
+ <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
+ fpga {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07400 0x00000100>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000001>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
+ <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
+ <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
+ <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
+ <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
+ <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
+ <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
+ <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
+ <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
+ <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
+ <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
+ <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
+ <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
+ <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
+ <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
+ <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
+ <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_noc_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_noc: noc at 0xffd10000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-noc";
+ reg = <0xffd10000 0x00008000>;
+ reg-names = "mpu_m0";
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
+ */
+ mpu0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
+ */
+ l3-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
+ */
+ fpga2sdram0-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
+ */
+ fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
+ */
+ fpga2sdram2-0 = <0x00000000 0x0000ffff>;
+ };
+ };
+
+ hps_fpgabridge0: fpgabridge at 0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge1: fpgabridge at 1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge2: fpgabridge at 2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge3: fpgabridge at 3 {
+ compatible = "altr,socfpga-fpga2sdram0-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge4: fpgabridge at 4 {
+ compatible = "altr,socfpga-fpga2sdram1-bridge";
+ init-val = <0>;
+ };
+
+ hps_fpgabridge5: fpgabridge at 5 {
+ compatible = "altr,socfpga-fpga2sdram2-bridge";
+ init-val = <1>;
+ };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 30b475254c..7e96b7e976 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -28,6 +28,10 @@ config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
+config TARGET_SOCFPGA_ARRIA10_R329
+ bool "Reflex CES SOCFPGA R329 PCIe (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -78,6 +82,7 @@ endchoice
config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "r329-a10-pcie" if TARGET_SOCFPGA_ARRIA10_R329
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -92,6 +97,7 @@ config SYS_BOARD
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "reflexces" if TARGET_SOCFPGA_ARRIA10_R329
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -107,6 +113,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "socfpga_r329_a10_pcie" if TARGET_SOCFPGA_ARRIA10_R329
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/board/reflexces/r329-a10-pcie/Kconfig b/board/reflexces/r329-a10-pcie/Kconfig
new file mode 100644
index 0000000000..fe4a0267e7
--- /dev/null
+++ b/board/reflexces/r329-a10-pcie/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "r329-a10-pcie"
+
+config SYS_VENDOR
+ default "reflexces"
+
+config SYS_SOC
+ default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+ default "socfpga_r329_a10_pcie"
+
+endif
diff --git a/board/reflexces/r329-a10-pcie/MAINTAINERS b/board/reflexces/r329-a10-pcie/MAINTAINERS
new file mode 100644
index 0000000000..0ed98d8023
--- /dev/null
+++ b/board/reflexces/r329-a10-pcie/MAINTAINERS
@@ -0,0 +1,8 @@
+R329 BOARD
+M: Xavier Ruppen <xruppen at gmail.com>
+S: Maintained
+F: board/reflexces/r329-a10-pcie/
+F: include/configs/socfpga_arria10_r329.h
+F: configs/socfpga_r329_a10_pcie_defconfig
+F: arch/arm/dts/socfpga_arria10_r329.dts
+F: arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
diff --git a/board/reflexces/r329-a10-pcie/Makefile b/board/reflexces/r329-a10-pcie/Makefile
new file mode 100644
index 0000000000..80d0004346
--- /dev/null
+++ b/board/reflexces/r329-a10-pcie/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+
+obj-y := socfpga.o
diff --git a/board/reflexces/r329-a10-pcie/fit_spl_fpga.its b/board/reflexces/r329-a10-pcie/fit_spl_fpga.its
new file mode 100644
index 0000000000..eb761263ab
--- /dev/null
+++ b/board/reflexces/r329-a10-pcie/fit_spl_fpga.its
@@ -0,0 +1,45 @@
+/*
+ * The fitImage source for Reflex CES R329 loading U-Boot with bitstream on EPCQ.
+ *
+ * Copyright (C) 2018 Xavier Ruppen <xruppen at gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (32-bit)";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm";
+ compression = "none";
+ load = <0x01000040>;
+ entry = <0x01000040>;
+ };
+
+ fdt {
+ description = "Reflex CES R329 flat device-tree";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ load = <0x00f00000>;
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Reflex CES R329 SOM-A10_PCIe";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/board/reflexces/r329-a10-pcie/socfpga.c b/board/reflexces/r329-a10-pcie/socfpga.c
new file mode 100644
index 0000000000..4c466cb944
--- /dev/null
+++ b/board/reflexces/r329-a10-pcie/socfpga.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
diff --git a/configs/socfpga_r329_a10_pcie_defconfig b/configs/socfpga_r329_a10_pcie_defconfig
new file mode 100644
index 0000000000..03f49f9587
--- /dev/null
+++ b/configs/socfpga_r329_a10_pcie_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x01000040
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TARGET_SOCFPGA_ARRIA10_R329=y
+CONFIG_SPL=y
+CONFIG_IDENT_STRING="socfpga_r329_a10_pcie"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_r329"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/reflexces/r329-a10-pcie/fit_spl_fpga.its"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_r329.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/include/configs/socfpga_r329_a10_pcie.h b/include/configs/socfpga_r329_a10_pcie.h
new file mode 100644
index 0000000000..a802ff585b
--- /dev/null
+++ b/include/configs/socfpga_r329_a10_pcie.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+
+/* Booting Linux */
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0xC0000000
+
+/* Ethernet on SoC (EMAC) */
+
+/*
+ * U-Boot environment configurations
+ */
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
--
2.17.1
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