[U-Boot] [linux-sunxi] [PATCH v2 10/13] sunxi: add MMC support for H6

[Jagan Teki]

On Sat, Jul 21, 2018 at 1:50 PM, Icenowy Zheng <icenowy at aosc.io> wrote:
> The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
> the MMC2 come with the capability to do crypto by EMCE.
>
> Add MMC support for H6. EMCE support is not added yet.
>
> Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
> ---
>  arch/arm/include/asm/arch-sunxi/mmc.h |  2 +-
>  board/sunxi/board.c                   |  7 +++++++
>  drivers/mmc/sunxi_mmc.c               | 13 ++++++++++++-
>  3 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 1574b8e8fe..d98c53faaa 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -45,7 +45,7 @@ struct sunxi_mmc {
>         u32 chda;               /* 0x90 */
>         u32 cbda;               /* 0x94 */
>         u32 res2[26];
> -#ifdef CONFIG_SUNXI_GEN_SUN6I
> +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
>         u32 res3[64];
>  #endif
>         u32 fifo;               /* 0x100 / 0x200 FIFO access address */
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 5ed1b8bae1..857d5ff010 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -443,6 +443,13 @@ static void mmc_pinmux_setup(int sdc)
>                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
>                         sunxi_gpio_set_drv(pin, 2);
>                 }
> +#elif defined(CONFIG_MACH_SUN50I_H6)
> +               /* SDC2: PC4-PC14 */
> +               for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
> +                       sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
> +                       sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> +                       sunxi_gpio_set_drv(pin, 2);
> +               }
>  #elif defined(CONFIG_MACH_SUN9I)
>                 /* SDC2: PC6-PC16 */
>                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 7fa1ae8b16..39f15eb423 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
>                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
>                 priv->mclkreg = &ccm->sd2_clk_cfg;
>                 break;
> +#ifdef SUNXI_MMC3_BASE
>         case 3:
>                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
>                 priv->mclkreg = &ccm->sd3_clk_cfg;
>                 break;
> +#endif
>         default:
>                 printf("Wrong mmc number %d\n", sdc_no);
>                 return -1;
> @@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
>  #ifdef CONFIG_MACH_SUN9I
>                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
>                 pll_hz = clock_get_pll4_periph0();
> +#elif defined(CONFIG_MACH_SUN50I_H6)
> +               pll = CCM_MMC_CTRL_PLL6X2;
> +               pll_hz = clock_get_pll6() * 2;
>  #else
>                 pll = CCM_MMC_CTRL_PLL6;
>                 pll_hz = clock_get_pll6();
> @@ -494,7 +499,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>
>         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
>         cfg->host_caps = MMC_MODE_4BIT;
> -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
>         if (sdc_no == 2)
>                 cfg->host_caps = MMC_MODE_8BIT;
>  #endif
> @@ -509,6 +514,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>
>         /* config ahb clock */
>         debug("init mmc %d clock and io\n", sdc_no);
> +#if !defined(CONFIG_MACH_SUN50I_H6)
>         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
>
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
> @@ -519,6 +525,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>         /* sun9i has a mmc-common module, also set the gate and reset there */
>         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
>                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
> +#endif
> +#else /* CONFIG_MACH_SUN50I_H6 */
> +       setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
> +       /* unassert reset */
> +       setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));

Set the ahb and reset directly in one call since we have a provision
of having same register in H6.

Reviewed-by: Jagan Teki <jagan at openedev.com>