[U-Boot] [PATCH v2 06/11] net: phy: ti: add workaround for incorrect RX_CTRL pin strap

[Joe Hershberger]

On Fri, Jul 20, 2018 at 6:00 PM, Grygorii Strashko
<grygorii.strashko at ti.com> wrote:
>
>
> On 07/18/2018 03:46 AM, Janine Hagemann wrote:
>>
>> The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
>> advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
>> supported (see note below Table 5 (4-Level Strap Pins)).
>>
>> There are some boards which have the pin strapped this way and need
>> software workaround suggested by the data manual. Bit[7] of
>> Configuration Register 4 (address 0x0031) must be cleared to 0. This
>> ensures proper operation of the PHY.
>>
>> Implement driver support for device-tree property meant to advertise
>> the wrong strapping.
>>
>> [1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
>>
>> Based on commit 371444764b98 ("net: phy: dp83867: add workaround for
>> incorrect RX_CTRL pin strap") of mainline linux kernel.
>>
>> Signed-off-by: Janine Hagemann <j.hagemann at phytec.de>
>> ---
>> v2: Change commit reference format
>> ---
>>   drivers/net/phy/ti.c | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
>> index ea1ee24..f0ca8f2 100644
>> --- a/drivers/net/phy/ti.c
>> +++ b/drivers/net/phy/ti.c
>> @@ -111,6 +111,7 @@ struct dp83867_private {
>>         int fifo_depth;
>>         int io_impedance;
>>         int port_mirroring;
>> +       bool rxctrl_strap_quirk;
>>   };
>>     /**
>> @@ -219,6 +220,9 @@ static int dp83867_of_init(struct phy_device *phydev)
>>         else
>>                 dp83867->io_impedance = -EINVAL;
>>   +     dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node,
>> +                                       "ti,dp83867-rxctrl-strap-quirk");
>> +
>>         dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob,
>> dev_of_offset(dev),
>>                                  "ti,rx-internal-delay", -1);
>>   @@ -274,6 +278,15 @@ static int dp83867_config(struct phy_device
>> *phydev)
>>         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
>>                   val | DP83867_SW_RESTART);
>>   +     /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
>> +       if (dp83867->rxctrl_strap_quirk) {
>> +               val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
>> +                                               DP83867_DEVADDR,
>> phydev->addr);
>> +               val &= ~BIT(7);
>> +               phy_write_mmd_indirect(phydev, DP83867_CFG4,
>> DP83867_DEVADDR,
>> +                                       phydev->addr, val);
>> +       }
>> +
>>         if (phy_interface_is_rgmii(phydev)) {
>>                 ret = phy_write(phydev, MDIO_DEVAD_NONE,
>> MII_DP83867_PHYCTRL,
>>                         (DP83867_MDI_CROSSOVER_AUTO <<
>> DP83867_MDI_CROSSOVER) |
>>
>
> Pls, check
> https://patchwork.ozlabs.org/cover/936370/
> and
> https://patchwork.ozlabs.org/cover/936380/
>
> i'd need to rebase your series.

These are now in my tree, so you could rebase on that and resend.

-Joe