[U-Boot] [PATCH v3 2/6] spi: omap3_spi: Full dm conversion
Hannes Schmelzer
Hannes.Schmelzer at br-automation.com
Sat Jun 2 08:49:20 UTC 2018
Jagan Teki <jagan at amarulasolutions.com> schrieb am 07.05.2018 11:17:42:
> Betreff: [PATCH v3 2/6] spi: omap3_spi: Full dm conversion
>
> omap3_spi now support dt along with platform data,
> respective boards need to switch into dm for the same.
>
> Tested-by: Adam Ford <aford173 at gmail.com> #omap3_logic
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
Hi Jagan,
Inspired by your patch i made some progess moving my AM335x boards to
driver model-
SPI flash isn't working there anymore quite ago.
I've sent some patches regarding this.
Have a look to:
https://patchwork.ozlabs.org/patch/924433/
Can you please review that?
Maybe we need to get things running again before we cann fully move to DM.
cheers,
Hannes
> ---
> drivers/spi/Kconfig | 14 +-
> drivers/spi/omap3_spi.c | 337
+++++++++++------------------------
> include/dm/platform_data/spi_omap3.h | 16 ++
> 3 files changed, 125 insertions(+), 242 deletions(-)
> create mode 100644 include/dm/platform_data/spi_omap3.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index d93f7d0049..72423beebf 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -111,6 +111,13 @@ config MVEBU_A3700_SPI
> used to access the SPI NOR flash on platforms embedding this
> Marvell IP core.
>
> +config OMAP3_SPI
> + bool "McSPI driver for OMAP"
> + help
> + SPI master controller for OMAP24XX and later Multichannel SPI
> + (McSPI). This driver be used to access SPI chips on platforms
> + embedding this OMAP3 McSPI IP core.
> +
> config PIC32_SPI
> bool "Microchip PIC32 SPI driver"
> depends on MACH_PIC32
> @@ -305,11 +312,4 @@ config MXS_SPI
> Enable the MXS SPI controller driver. This driver can be used
> on the i.MX23 and i.MX28 SoCs.
>
> -config OMAP3_SPI
> - bool "McSPI driver for OMAP"
> - help
> - SPI master controller for OMAP24XX and later Multichannel SPI
> - (McSPI). This driver be used to access SPI chips on platforms
> - embedding this OMAP3 McSPI IP core.
> -
> endmenu # menu "SPI Support"
> diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
> index 1ac691a68e..4108dcabbf 100644
> --- a/drivers/spi/omap3_spi.c
> +++ b/drivers/spi/omap3_spi.c
> @@ -22,6 +22,7 @@
> #include <spi.h>
> #include <malloc.h>
> #include <asm/io.h>
> +#include <dm/platform_data/spi_omap3.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -109,9 +110,6 @@ struct mcspi {
> };
>
> struct omap3_spi_priv {
> -#ifndef CONFIG_DM_SPI
> - struct spi_slave slave;
> -#endif
> struct mcspi *regs;
> unsigned int cs;
> unsigned int freq;
> @@ -312,12 +310,16 @@ static int omap3_spi_txrx(struct omap3_spi_priv
*priv,
> unsigned int len,
> return 0;
> }
>
> -static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
> - const void *dout, void *din, unsigned long flags)
> +static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
> {
> - unsigned int len;
> + struct udevice *bus = dev->parent;
> + struct omap3_spi_priv *priv = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
> + unsigned int len;
> int ret = -1;
>
> + priv->cs = slave_plat->cs;
> if (priv->wordlen < 4 || priv->wordlen > 32) {
> printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
> return -1;
> @@ -353,78 +355,6 @@ static int _spi_xfer(struct omap3_spi_priv *priv,
> unsigned int bitlen,
> return ret;
> }
>
> -static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
> -{
> - uint32_t confr, div = 0;
> -
> - confr = readl(&priv->regs->channel[priv->cs].chconf);
> -
> - /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
> - if (priv->freq) {
> - while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
> - > priv->freq)
> - div++;
> - } else {
> - div = 0xC;
> - }
> -
> - /* set clock divisor */
> - confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
> - confr |= div << 2;
> -
> - omap3_spi_write_chconf(priv, confr);
> -}
> -
> -static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
> -{
> - uint32_t confr;
> -
> - confr = readl(&priv->regs->channel[priv->cs].chconf);
> -
> - /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
> - * REVISIT: this controller could support SPI_3WIRE mode.
> - */
> - if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
> - confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
> - confr |= OMAP3_MCSPI_CHCONF_DPE0;
> - } else {
> - confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
> - confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
> - }
> -
> - /* set SPI mode 0..3 */
> - confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
> - if (priv->mode & SPI_CPHA)
> - confr |= OMAP3_MCSPI_CHCONF_PHA;
> - if (priv->mode & SPI_CPOL)
> - confr |= OMAP3_MCSPI_CHCONF_POL;
> -
> - /* set chipselect polarity; manage with FORCE */
> - if (!(priv->mode & SPI_CS_HIGH))
> - confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
> - else
> - confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
> -
> - /* Transmit & receive mode */
> - confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
> -
> - omap3_spi_write_chconf(priv, confr);
> -}
> -
> -static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
> -{
> - unsigned int confr;
> -
> - /* McSPI individual channel configuration */
> - confr = readl(&priv->regs->channel[priv->wordlen].chconf);
> -
> - /* wordlength */
> - confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
> - confr |= (priv->wordlen - 1) << 7;
> -
> - omap3_spi_write_chconf(priv, confr);
> -}
> -
> static void spi_reset(struct mcspi *regs)
> {
> unsigned int tmp;
> @@ -441,8 +371,10 @@ static void spi_reset(struct mcspi *regs)
> writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable);
> }
>
> -static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
> +static int omap3_spi_claim_bus(struct udevice *dev)
> {
> + struct udevice *bus = dev->parent;
> + struct omap3_spi_priv *priv = dev_get_priv(bus);
> unsigned int conf;
>
> spi_reset(priv->regs);
> @@ -456,142 +388,6 @@ static void _omap3_spi_claim_bus(struct
omap3_spi_priv *priv)
> conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
>
> writel(conf, &priv->regs->modulctrl);
> -}
> -
> -#ifndef CONFIG_DM_SPI
> -
> -static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave
*slave)
> -{
> - return container_of(slave, struct omap3_spi_priv, slave);
> -}
> -
> -void spi_init(void)
> -{
> - /* do nothing */
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> -{
> - struct omap3_spi_priv *priv = to_omap3_spi(slave);
> -
> - free(priv);
> -}
> -
> -int spi_claim_bus(struct spi_slave *slave)
> -{
> - struct omap3_spi_priv *priv = to_omap3_spi(slave);
> -
> - _omap3_spi_claim_bus(priv);
> - _omap3_spi_set_wordlen(priv);
> - _omap3_spi_set_mode(priv);
> - _omap3_spi_set_speed(priv);
> -
> - return 0;
> -}
> -
> -void spi_release_bus(struct spi_slave *slave)
> -{
> - struct omap3_spi_priv *priv = to_omap3_spi(slave);
> -
> - /* Reset the SPI hardware */
> - spi_reset(priv->regs);
> -}
> -
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> - unsigned int max_hz, unsigned int mode)
> -{
> - struct omap3_spi_priv *priv;
> - struct mcspi *regs;
> -
> - /*
> - * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
> - * with different number of chip selects (CS, channels):
> - * McSPI1 has 4 CS (bus 0, cs 0 - 3)
> - * McSPI2 has 2 CS (bus 1, cs 0 - 1)
> - * McSPI3 has 2 CS (bus 2, cs 0 - 1)
> - * McSPI4 has 1 CS (bus 3, cs 0)
> - */
> -
> - switch (bus) {
> - case 0:
> - regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
> - break;
> -#ifdef OMAP3_MCSPI2_BASE
> - case 1:
> - regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
> - break;
> -#endif
> -#ifdef OMAP3_MCSPI3_BASE
> - case 2:
> - regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
> - break;
> -#endif
> -#ifdef OMAP3_MCSPI4_BASE
> - case 3:
> - regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
> - break;
> -#endif
> - default:
> - printf("SPI error: unsupported bus %i. Supported busses 0 -
3\n", bus);
> - return NULL;
> - }
> -
> - if (((bus == 0) && (cs > 3)) ||
> - ((bus == 1) && (cs > 1)) ||
> - ((bus == 2) && (cs > 1)) ||
> - ((bus == 3) && (cs > 0))) {
> - printf("SPI error: unsupported chip select %i on bus %i\n", cs,
bus);
> - return NULL;
> - }
> -
> - if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
> - printf("SPI error: unsupported frequency %i Hz. Max frequency is
48 MHz\n",
> - max_hz);
> - return NULL;
> - }
> -
> - if (mode > SPI_MODE_3) {
> - printf("SPI error: unsupported SPI mode %i\n", mode);
> - return NULL;
> - }
> -
> - priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
> - if (!priv) {
> - printf("SPI error: malloc of SPI structure failed\n");
> - return NULL;
> - }
> -
> - priv->regs = regs;
> - priv->cs = cs;
> - priv->freq = max_hz;
> - priv->mode = mode;
> - priv->wordlen = priv->slave.wordlen;
> -#if 0
> - /* Please migrate to DM_SPI support for this feature. */
> - priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
> -#endif
> -
> - return &priv->slave;
> -}
> -
> -int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
> - const void *dout, void *din, unsigned long flags)
> -{
> - struct omap3_spi_priv *priv = to_omap3_spi(slave);
> -
> - return _spi_xfer(priv, bitlen, dout, din, flags);
> -}
> -
> -#else
> -
> -static int omap3_spi_claim_bus(struct udevice *dev)
> -{
> - struct udevice *bus = dev->parent;
> - struct omap3_spi_priv *priv = dev_get_priv(bus);
> - struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
> -
> - priv->cs = slave_plat->cs;
> - _omap3_spi_claim_bus(priv);
>
> return 0;
> }
> @@ -612,22 +408,31 @@ static int omap3_spi_set_wordlen(struct udevice
*dev,
> unsigned int wordlen)
> struct udevice *bus = dev->parent;
> struct omap3_spi_priv *priv = dev_get_priv(bus);
> struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
> + unsigned int confr;
> +
> + /* McSPI individual channel configuration */
> + confr = readl(&priv->regs->channel[wordlen].chconf);
> +
> + /* wordlength */
> + confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
> + confr |= (wordlen - 1) << 7;
>
> priv->cs = slave_plat->cs;
> + omap3_spi_write_chconf(priv, confr);
> +
> priv->wordlen = wordlen;
> - _omap3_spi_set_wordlen(priv);
>
> return 0;
> }
>
> static int omap3_spi_probe(struct udevice *dev)
> {
> + struct omap3_spi_platdata *plat = dev->platdata;
> struct omap3_spi_priv *priv = dev_get_priv(dev);
> - const void *blob = gd->fdt_blob;
> - int node = dev_of_offset(dev);
>
> - struct omap2_mcspi_platform_config* data =
> - (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
> + priv->regs = plat->regs;
> + priv->pin_dir = plat->pin_dir;
> + priv->wordlen = plat->wordlen;
>
> priv->regs = (struct mcspi *)(devfdt_get_addr(dev) +
data->regs_offset);
> if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
> @@ -635,16 +440,8 @@ static int omap3_spi_probe(struct udevice *dev)
> else
> priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
> priv->wordlen = SPI_DEFAULT_WORDLEN;
> - return 0;
> -}
> -
> -static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
> - const void *dout, void *din, unsigned long flags)
> -{
> - struct udevice *bus = dev->parent;
> - struct omap3_spi_priv *priv = dev_get_priv(bus);
>
> - return _spi_xfer(priv, bitlen, dout, din, flags);
> + return 0;
> }
>
> static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
> @@ -652,10 +449,25 @@ static int omap3_spi_set_speed(struct udevice
*dev,
> unsigned int speed)
> struct udevice *bus = dev->parent;
> struct omap3_spi_priv *priv = dev_get_priv(bus);
> struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
> + uint32_t confr, div = 0;
>
> priv->cs = slave_plat->cs;
> - priv->freq = slave_plat->max_hz;
> - _omap3_spi_set_speed(priv);
> + confr = readl(&priv->regs->channel[priv->cs].chconf);
> +
> + /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
> + if (speed) {
> + while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
> + > speed)
> + div++;
> + } else {
> + div = 0xC;
> + }
> +
> + /* set clock divisor */
> + confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
> + confr |= div << 2;
> +
> + omap3_spi_write_chconf(priv, confr);
>
> return 0;
> }
> @@ -665,10 +477,39 @@ static int omap3_spi_set_mode(struct udevice *dev,
uint mode)
> struct udevice *bus = dev->parent;
> struct omap3_spi_priv *priv = dev_get_priv(bus);
> struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
> + uint32_t confr;
>
> priv->cs = slave_plat->cs;
> - priv->mode = slave_plat->mode;
> - _omap3_spi_set_mode(priv);
> + confr = readl(&priv->regs->channel[priv->cs].chconf);
> +
> + /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
> + * REVISIT: this controller could support SPI_3WIRE mode.
> + */
> + if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
> + confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
> + confr |= OMAP3_MCSPI_CHCONF_DPE0;
> + } else {
> + confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
> + confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
> + }
> +
> + /* set SPI mode 0..3 */
> + confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
> + if (mode & SPI_CPHA)
> + confr |= OMAP3_MCSPI_CHCONF_PHA;
> + if (mode & SPI_CPOL)
> + confr |= OMAP3_MCSPI_CHCONF_POL;
> +
> + /* set chipselect polarity; manage with FORCE */
> + if (!(mode & SPI_CS_HIGH))
> + confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
> + else
> + confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
> +
> + /* Transmit & receive mode */
> + confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
> +
> + omap3_spi_write_chconf(priv, confr);
>
> return 0;
> }
> @@ -677,7 +518,7 @@ static const struct dm_spi_ops omap3_spi_ops = {
> .claim_bus = omap3_spi_claim_bus,
> .release_bus = omap3_spi_release_bus,
> .set_wordlen = omap3_spi_set_wordlen,
> - .xfer = omap3_spi_xfer,
> + .xfer = omap3_spi_xfer,
> .set_speed = omap3_spi_set_speed,
> .set_mode = omap3_spi_set_mode,
> /*
> @@ -686,6 +527,28 @@ static const struct dm_spi_ops omap3_spi_ops = {
> */
> };
>
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> +static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct omap3_spi_platdata *plat = dev->platdata;
> + struct omap2_mcspi_platform_config* data =
> + (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
> + fdt_addr_t addr;
> +
> + addr = devfdt_get_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + plat->regs = (struct mcspi *)addr;
> + plat->regs += data->regs_offset;
> + plat->pin_dir = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> + "ti,pindir-d0-out-d1-in",
> + MCSPI_PINDIR_D0_IN_D1_OUT);
> + plat->wordlen = SPI_DEFAULT_WORDLEN;
> +
> + return 0;
> +}
> +
> static struct omap2_mcspi_platform_config omap2_pdata = {
> .regs_offset = 0,
> };
> @@ -699,13 +562,17 @@ static const struct udevice_id omap3_spi_ids[] = {
> { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
> { }
> };
> +#endif
>
> U_BOOT_DRIVER(omap3_spi) = {
> .name = "omap3_spi",
> .id = UCLASS_SPI,
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> .of_match = omap3_spi_ids,
> + .ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct omap3_spi_platdata),
> +#endif
> .probe = omap3_spi_probe,
> .ops = &omap3_spi_ops,
> .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
> };
> -#endif
> diff --git a/include/dm/platform_data/spi_omap3.h
b/include/dm/platform_data/spi_omap3.h
> new file mode 100644
> index 0000000000..9323266de7
> --- /dev/null
> +++ b/include/dm/platform_data/spi_omap3.h
> @@ -0,0 +1,16 @@
> +/*
> + * Copyright (C) 2018 Jagan Teki <jagan at amarulasolutions.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __spi_omap3_h
> +#define __spi_omap3_h
> +
> +struct omap3_spi_platdata {
> + struct mcspi *regs;
> + unsigned int wordlen;
> + unsigned int pin_dir:1;
> +};
> +
> +#endif /* __spi_omap3_h */
> --
> 2.14.3
>
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