[U-Boot] [PATCH 10/12] net: phy: ti: Add binding for the CLK_OUT pin muxing

[Joe Hershberger]

On Thu, Jun 14, 2018 at 4:48 AM, Janine Hagemann <j.hagemann at phytec.de> wrote:
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
>
> Based on commit '9708fb630d19ee51ae3aeb3a533e3010da0e8570' mainline
> linux kernel.

Same here...

> Signed-off-by: Janine Hagemann <j.hagemann at phytec.de>
> ---
>  drivers/net/phy/ti.c                 | 24 ++++++++++++++++++++++++
>  include/dt-bindings/net/ti-dp83867.h | 15 +++++++++++++++

Please also add to doc/device-tree-bindings/net/ti,dp83867.txt

>  2 files changed, 39 insertions(+)
>
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index cc04789..9044b0f 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX    0x0
>  #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN    0x1f
> +#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK      (0x1f << 8)
> +#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT     8

Reverse order of these defines and use the shift to make the mask.

Also, use GENMASK(13, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)

>
>  /* CFG4 bits */
>  #define DP83867_CFG4_PORT_MIRROR_EN            BIT(0)
> @@ -113,6 +115,7 @@ struct dp83867_private {
>         int io_impedance;
>         int port_mirroring;
>         bool rxctrl_strap_quirk;
> +       int clk_output_sel;
>  };
>
>  /**
> @@ -213,6 +216,16 @@ static int dp83867_of_init(struct phy_device *phydev)
>         struct udevice *dev = phydev->dev;
>         int node = dev_of_offset(dev);
>         const void *fdt = gd->fdt_blob;
> +       u16 val;
> +
> +       /* Optional configuration */
> +
> +       /* Keep the default value if ti,clk-output-sel is not set

Please use standard mutli-line comment format.... "/*" gets its own line.

> +        * or to high
> +        */
> +
> +       dp83867->clk_output_sel = fdtdec_get_uint(fdt, node,
> +                                                 "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
>
>         if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
>                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> @@ -239,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev)
>         dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
>                                  "ti,fifo-depth", -1);
>
> +       /* Clock output selection if muxing property is set */
> +       if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
> +               val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
> +                                           DP83867_DEVADDR, phydev->addr);
> +               val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
> +               val |= (dp83867->clk_output_sel <<
> +                       DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
> +               phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
> +                                       DP83867_DEVADDR, phydev->addr, val);
> +       }
> +
>         return 0;
>  }
>  #else
> diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
> index b8e5df6..85d08f6 100644
> --- a/include/dt-bindings/net/ti-dp83867.h
> +++ b/include/dt-bindings/net/ti-dp83867.h
> @@ -31,4 +31,19 @@
>  #define DP83867_RGMIIDCTL_3_75_NS      0xe
>  #define DP83867_RGMIIDCTL_4_00_NS      0xf
>
> +/* IO_MUX_CFG - Clock output selection */
> +#define DP83867_CLK_O_SEL_CHN_A_RCLK           0x0
> +#define DP83867_CLK_O_SEL_CHN_B_RCLK           0x1
> +#define DP83867_CLK_O_SEL_CHN_C_RCLK           0x2
> +#define DP83867_CLK_O_SEL_CHN_D_RCLK           0x3
> +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5      0x4
> +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5      0x5
> +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5      0x6
> +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5      0x7
> +#define DP83867_CLK_O_SEL_CHN_A_TCLK           0x8
> +#define DP83867_CLK_O_SEL_CHN_B_TCLK           0x9
> +#define DP83867_CLK_O_SEL_CHN_C_TCLK           0xA
> +#define DP83867_CLK_O_SEL_CHN_D_TCLK           0xB
> +#define DP83867_CLK_O_SEL_REF_CLK              0xC
> +
>  #endif
> --
> 2.7.4
>
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