[U-Boot] [PATCH v3 2/3] efi_loader: ARM: run EFI payloads non-secure

Mark Kettenis mark.kettenis at xs4all.nl
Thu Jun 14 20:55:17 UTC 2018


> From: Marc Zyngier <marc.zyngier at arm.com>
> Date: Thu, 14 Jun 2018 12:54:53 +0100
> 
> On 13/06/18 23:41, Mark Kettenis wrote:
> > If desired (and possible) switch into HYP mode or non-secure SVC mode
> > before calling the entry point of an EFI application.  This allows
> > U-Boot to provide a usable PSCI implementation and makes it possible
> > to boot kernels into hypervisor mode using an EFI bootloader.
> > 
> > Based on diffs from Heinrich Schuchardt and Alexander Graf.
> > 
> > Signed-off-by: Mark Kettenis <kettenis at openbsd.org>
> > ---
> >  cmd/bootefi.c | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> > 
> > diff --git a/cmd/bootefi.c b/cmd/bootefi.c
> > index 707d159bac..12a6b84ce6 100644
> > --- a/cmd/bootefi.c
> > +++ b/cmd/bootefi.c
> > @@ -20,6 +20,11 @@
> >  #include <asm-generic/unaligned.h>
> >  #include <linux/linkage.h>
> >  
> > +#ifdef CONFIG_ARMV7_NONSEC
> > +#include <asm/armv7.h>
> > +#include <asm/secure.h>
> > +#endif
> > +
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> >  #define OBJ_LIST_NOT_INITIALIZED 1
> > @@ -189,6 +194,18 @@ static efi_status_t efi_run_in_el2(EFIAPI efi_status_t (*entry)(
> >  }
> >  #endif
> >  
> > +#ifdef CONFIG_ARMV7_NONSEC
> > +static efi_status_t efi_run_in_hyp(EFIAPI efi_status_t (*entry)(
> > +			efi_handle_t image_handle, struct efi_system_table *st),
> > +			efi_handle_t image_handle, struct efi_system_table *st)
> > +{
> > +	/* Enable caches again */
> > +	dcache_enable();
> > +
> > +	return efi_do_enter(image_handle, st, entry);
> > +}
> > +#endif
> > +
> >  /* Carve out DT reserved memory ranges */
> >  static efi_status_t efi_carve_out_dt_rsv(void *fdt)
> >  {
> > @@ -338,6 +355,21 @@ static efi_status_t do_bootefi_exec(void *efi,
> >  	}
> >  #endif
> >  
> > +#ifdef CONFIG_ARMV7_NONSEC
> > +	if (armv7_boot_nonsec()) {
> > +		dcache_disable();	/* flush cache before switch to HYP */
> > +
> 
> What is the rational for disabling/enabling caches across the transition
> to HYP? I'm sure there is a good reason, but I'd rather see it explained
> here.

Can't say I fully understan why.  But the AArch64 code does this as
well and if I don't flush the cache here the contents of efi_gd (which
gets initialized before the switch) sometimes gets lost.

> > +		armv7_init_nonsec();
> > +		secure_ram_addr(_do_nonsec_entry)(efi_run_in_hyp,
> > +				(uintptr_t)entry,
> > +				(uintptr_t)loaded_image_info_obj.handle,
> > +				(uintptr_t)&systab);
> > +
> > +		/* Should never reach here, efi exits with longjmp */
> > +		while (1) { }
> > +	}
> > +#endif
> > +
> >  	ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry);
> >  
> >  exit:
> > 


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