[U-Boot] [PATCH] imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms

[Stefano Babic]

On 14/05/2018 14:44, Fabio Estevam wrote:
> From: Ye Li <ye.li at nxp.com>
> 
> According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
> is set to 1 before the caches and MMU are enabled, or any cache and TLB
> maintenance operations are performed".
> ROM sets this bit in normal boot flow, but when in serial download mode,
> it is not set.
> Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
> including mx7d, mx6ul/ull and mx7ulp.
> 
> Signed-off-by: Ye Li <ye.li at nxp.com>
> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy]
> Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
> ---
>  arch/arm/mach-imx/cache.c   | 42 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/mx7/soc.c |  7 -------
>  2 files changed, 42 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
> index c5279a7..86205cf 100644
> --- a/arch/arm/mach-imx/cache.c
> +++ b/arch/arm/mach-imx/cache.c
> @@ -10,6 +10,34 @@
>  #include <asm/io.h>
>  #include <asm/mach-imx/sys_proto.h>
>  
> +static void enable_ca7_smp(void)
> +{
> +	u32 val;
> +
> +	/* Read MIDR */
> +	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
> +	val = (val >> 4);
> +	val &= 0xf;
> +
> +	/* Only set the SMP for Cortex A7 */
> +	if (val == 0x7) {
> +		/* Read auxiliary control register */
> +		asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
> +
> +		if (val & (1 << 6))
> +			return;
> +
> +		/* Enable SMP */
> +		val |= (1 << 6);
> +
> +		/* Write auxiliary control register */
> +		asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
> +
> +		DSB;
> +		ISB;
> +	}
> +}
> +
>  #ifndef CONFIG_SYS_DCACHE_OFF
>  void enable_caches(void)
>  {
> @@ -21,6 +49,9 @@ void enable_caches(void)
>  	/* Avoid random hang when download by usb */
>  	invalidate_dcache_all();
>  
> +	/* Set ACTLR.SMP bit for Cortex-A7 */
> +	enable_ca7_smp();
> +
>  	/* Enable D-cache. I-cache is already enabled in start.S */
>  	dcache_enable();
>  
> @@ -32,6 +63,17 @@ void enable_caches(void)
>  					IRAM_SIZE,
>  					option);
>  }
> +#else
> +void enable_caches(void)
> +{
> +	/*
> +	 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
> +	 * disabled by u-boot
> +	 */
> +	enable_ca7_smp();
> +
> +	puts("WARNING: Caches not enabled\n");
> +}
>  #endif
>  
>  #ifndef CONFIG_SYS_L2CACHE_OFF
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 3ceeeff..83bcd2d 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -281,13 +281,6 @@ const struct boot_mode soc_boot_modes[] = {
>  
>  void s_init(void)
>  {
> -#if !defined CONFIG_SPL_BUILD
> -	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
> -	asm volatile(
> -			"mrc p15, 0, r0, c1, c0, 1\n"
> -			"orr r0, r0, #1 << 6\n"
> -			"mcr p15, 0, r0, c1, c0, 1\n");
> -#endif
>  	/* clock configuration. */
>  	clock_init();
>  
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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