[U-Boot] [PATCH] mtd: nand: denali: Replace the ad-hoc cache management with bouncebuf
Masahiro Yamada
yamada.masahiro at socionext.com
Tue Jun 19 06:39:11 UTC 2018
Hi Marek,
2018-06-08 5:17 GMT+09:00 Marek Vasut <marex at denx.de>:
> Replace the ad-hoc DMA cache management functions with common bouncebuf,
> since those functions are not handling cases where unaligned buffer is
> passed in,
Were you hit by a problem,
or just-in-case replacement?
I thought I took care of the buffer alignment.
The bounce buffer is allocated by kmalloc():
https://github.com/u-boot/u-boot/blob/v2018.05/drivers/mtd/nand/denali.c#L1348
According to the lib/linux_compat.c implementation,
it returns memory aligned with ARCH_DMA_MINALIGN.
If the buffer is passed from the upper MTD layer,
the NAND core also makes sure the enough alignment:
https://github.com/u-boot/u-boot/blob/v2018.05/drivers/mtd/nand/denali.c#L1273
This is how this driver works in Linux.
I'd rather want to keep the current code
unless this is a real problem,
One possible clean-up is to move dma_(un)map_single to a common place.
> while common bouncebuf does handle all that.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Masahiro Yamada <yamada.masahiro at socionext.com>
> Cc: Tom Rini <trini at konsulko.com>
> ---
> drivers/mtd/nand/denali.c | 41 +++++++----------------------------------
> 1 file changed, 7 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
> index 089ebce6dd..e5e84a58aa 100644
> --- a/drivers/mtd/nand/denali.c
> +++ b/drivers/mtd/nand/denali.c
> @@ -5,6 +5,7 @@
> * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
> */
>
> +#include <bouncebuf.h>
> #include <dm.h>
> #include <nand.h>
> #include <linux/bitfield.h>
> @@ -16,31 +17,6 @@
>
> #include "denali.h"
>
> -static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
> - enum dma_data_direction dir)
> -{
> - unsigned long addr = (unsigned long)ptr;
> -
> - if (dir == DMA_FROM_DEVICE)
> - invalidate_dcache_range(addr, addr + size);
> - else
> - flush_dcache_range(addr, addr + size);
> -
> - return addr;
> -}
> -
> -static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
> - enum dma_data_direction dir)
> -{
> - if (dir != DMA_TO_DEVICE)
> - invalidate_dcache_range(addr, addr + size);
> -}
> -
> -static int dma_mapping_error(void *dev, dma_addr_t addr)
> -{
> - return 0;
> -}
> -
> #define DENALI_NAND_NAME "denali-nand"
>
> /* for Indexed Addressing */
> @@ -563,16 +539,12 @@ static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
> static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
> size_t size, int page, int raw, int write)
> {
> - dma_addr_t dma_addr;
> uint32_t irq_mask, irq_status, ecc_err_mask;
> - enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
> + unsigned int bbflags = write ? GEN_BB_READ : GEN_BB_WRITE;
> + struct bounce_buffer bbstate;
> int ret = 0;
>
> - dma_addr = dma_map_single(denali->dev, buf, size, dir);
> - if (dma_mapping_error(denali->dev, dma_addr)) {
> - dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
> - return denali_pio_xfer(denali, buf, size, page, raw, write);
> - }
> + bounce_buffer_start(&bbstate, buf, size, bbflags);
>
> if (write) {
> /*
> @@ -593,7 +565,8 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
> iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
>
> denali_reset_irq(denali);
> - denali->setup_dma(denali, dma_addr, page, write);
> + denali->setup_dma(denali, virt_to_phys(bbstate.bounce_buffer),
> + page, write);
>
> irq_status = denali_wait_for_irq(denali, irq_mask);
> if (!(irq_status & INTR__DMA_CMD_COMP))
> @@ -603,7 +576,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
>
> iowrite32(0, denali->reg + DMA_ENABLE);
>
> - dma_unmap_single(denali->dev, dma_addr, size, dir);
> + bounce_buffer_stop(&bbstate);
>
> if (irq_status & INTR__ERASED_PAGE)
> memset(buf, 0xff, size);
> --
> 2.16.2
>
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--
Best Regards
Masahiro Yamada
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