[U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn at gmail.com> 於 2018年11月4日 週日 下午10:31寫道：
>
> Hi Rick,
>
> On Thu, Nov 1, 2018 at 12:10 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
> > AndeStar RISC-V(V5) provide mcache_ctl register which
> > can configure I/D cache as enabled or disabled.
> >
> > This CSR will be encapsulated by CONFIG_RISCV_NDS.
> > If you want to configure cache on AndeStar V5
> > AE350 platform. YOu can enable [*] AndeStar V5 ISA support
> > by make menuconfig.
> >
> > This approach also provide the expansion when the
> > vender specific features are going to join in.
> >
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > Cc: Greentime Hu <greentime at andestech.com>
> > ---
> >  arch/riscv/Kconfig             |  8 ++++
> >  arch/riscv/cpu/ax25/Makefile   |  1 +
> >  arch/riscv/cpu/ax25/cache.c    | 89 ++++++++++++++++++++++++++++++++++++++++++
> >  arch/riscv/cpu/ax25/cpu.c      |  4 ++
> >  arch/riscv/cpu/qemu/cpu.c      |  2 +-
> >  arch/riscv/cpu/start.S         |  6 +++
> >  arch/riscv/include/asm/cache.h |  9 +++++
> >  arch/riscv/lib/cache.c         | 30 +++++++++-----
> >  8 files changed, 138 insertions(+), 11 deletions(-)
> >  create mode 100644 arch/riscv/cpu/ax25/cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 371921b..a356729 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -74,4 +74,12 @@ config 32BIT
> >  config 64BIT
> >         bool
> >
> > +config RISCV_NDS
>
> This needs better be moved to arch/riscv/cpu/ax25/Kconfig. I have a
> patch to organize the Kconfig options in a hierarchy way @

I will move this to arch/riscv/cpu/ax25/Kconfig

> http://git.denx.de/?p=u-boot/u-boot-x86.git;a=commitdiff;h=5a650689410482907a37f77b2a4257d81bb4daa2;hp=11f2be3a168230d6e3afddb75b1a63adb0c1b838
>
> > +       bool "AndeStar V5 ISA support"
> > +       default n
>
> nits: default n is not needed.

It may still needed.
Or it will fail in auto build with generic RISC-V toolchain.
It do not recognize this mcache_ctl csr .

>
> If we move this to arch/riscv/cpu/ax25/Kconfig, this option can be
> selected by the board config.
>
> > +       help
> > +               Say Y here if you plan to run U-Boot on AndeStar v5
> > +               platforms and use some specific features which are
> > +               provided by Andes Technology AndeStar V5 Families.
> > +
> >  endmenu
> > diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
> > index 2ab0342..318bacc 100644
> > --- a/arch/riscv/cpu/ax25/Makefile
> > +++ b/arch/riscv/cpu/ax25/Makefile
> > @@ -4,3 +4,4 @@
> >  # Rick Chen, Andes Technology Corporation <rick at andestech.com>
> >
> >  obj-y  := cpu.o
> > +obj-y  += cache.o
> > diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> > new file mode 100644
> > index 0000000..e0bcaa2
> > --- /dev/null
> > +++ b/arch/riscv/cpu/ax25/cache.c
> > @@ -0,0 +1,89 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2017 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation <rick at andestech.com>
> > + */
> > +
> > +#include <common.h>
> > +
> > +void icache_enable(void)
> > +{
> > +#ifndef CONFIG_SYS_ICACHE_OFF
> > +#ifdef CONFIG_RISCV_NDS
>
> There is no need to #ifdef here.
>
> > +       asm volatile (
> > +               "csrr t1, mcache_ctl\n\t"
> > +               "ori t0, t1, 0x1\n\t"
> > +               "csrw mcache_ctl, t0\n\t"
> > +       );
> > +#endif
> > +#endif
> > +}
> > +
>
> [snip]
>
> Regards,
> Bin