[U-Boot] [PATCH 1/3] riscv: Add kconfig option to run u-boot in S-mode

[Anup Patel]

This patch adds kconfig option RISCV_SMODE to run u-boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.

It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.

Eventually, we will have patches to avoid accessing misa and
mhartid from S-mode.

Signed-off-by: Anup Patel <anup at brainfault.org>
---
 arch/riscv/Kconfig     |  6 ++++++
 arch/riscv/cpu/start.S | 31 +++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 168ca3de7c..0ee3bcc3c5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -37,6 +37,12 @@ config CPU_RISCV_64
 
 endchoice
 
+config RISCV_SMODE
+	bool "Run in S-Mode"
+	default n
+	help
+	  Enable this option to build an U-Boot for RISC-V S-Mode
+
 config 32BIT
 	bool
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 7cd7755190..669d3bde92 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -47,9 +47,15 @@ handle_reset:
 	li t0, CONFIG_SYS_SDRAM_BASE
 	SREG a2, 0(t0)
 	la t0, trap_entry
+#ifdef CONFIG_RISCV_SMODE
+	csrw stvec, t0
+	csrwi sstatus, 0
+	csrwi sie, 0
+#else
 	csrw mtvec, t0
 	csrwi mstatus, 0
 	csrwi mie, 0
+#endif
 
 /*
  * Do CPU critical regs init only at reboot,
@@ -171,7 +177,11 @@ fix_rela_dyn:
 */
 	la t0, trap_entry
 	add t0, t0, t6
+#ifdef CONFIG_RISCV_SMODE
+	csrw stvec, t0
+#else
 	csrw mtvec, t0
+#endif
 
 clear_bss:
 	la t0, __bss_start		/* t0 <- rel __bss_start in FLASH */
@@ -241,17 +251,34 @@ trap_entry:
 	SREG x29, 29*REGBYTES(sp)
 	SREG x30, 30*REGBYTES(sp)
 	SREG x31, 31*REGBYTES(sp)
+#ifdef CONFIG_RISCV_SMODE
+	csrr a0, scause
+	csrr a1, sepc
+#else
 	csrr a0, mcause
 	csrr a1, mepc
+#endif
 	mv a2, sp
 	jal handle_trap
+#ifdef CONFIG_RISCV_SMODE
+	csrw sepc, a0
+#else
 	csrw mepc, a0
+#endif
 
+#ifdef CONFIG_RISCV_SMODE
+/*
+ * Remain in S-mode after sret
+ */
+	li t0, SSTATUS_SPP
+	csrs sstatus, t0
+#else
 /*
  * Remain in M-mode after mret
  */
 	li t0, MSTATUS_MPP
 	csrs mstatus, t0
+#endif
 	LREG x1, 1*REGBYTES(sp)
 	LREG x2, 2*REGBYTES(sp)
 	LREG x3, 3*REGBYTES(sp)
@@ -284,7 +311,11 @@ trap_entry:
 	LREG x30, 30*REGBYTES(sp)
 	LREG x31, 31*REGBYTES(sp)
 	addi sp, sp, 32*REGBYTES
+#ifdef CONFIG_RISCV_SMODE
+	sret
+#else
 	mret
+#endif
 
 #ifdef CONFIG_INIT_CRITICAL
 cpu_init_crit:
-- 
2.17.1