[U-Boot] [PATCHv2 1/8] armv8: fsl-layerscpae: correct the PCIe controllers' region size

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - No change

 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index eaa9ed251e..b4bd2c604a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -34,10 +34,17 @@
 #define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
+#ifdef CONFIG_ARCH_LS2080A
 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
 #define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#else
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#endif
 #define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
-- 
2.17.1