[U-Boot] [PATCH] arm: socfpga: crc-protect SPL on warm boot

[Marek Vasut]

On 11/21/2018 06:13 AM, Simon Goldschmidt wrote:
> 
> 
> Am Mi., 21. Nov. 2018, 00:12 hat Marek Vasut <marex at denx.de
> <mailto:marex at denx.de>> geschrieben:
> 
>     On 11/20/2018 10:55 PM, Dalon L Westergreen wrote:
>     > On Tue, 2018-11-20 at 21:54 +0100, Simon Goldschmidt wrote:
>     >> On 20.11.2018 20:33, Marek Vasut wrote:
>     >>> On 11/20/2018 08:22 PM, Simon Goldschmidt wrote:
>     >>>> From: Simon Goldschmidt <sgoldschmidt at de.pepperl-fuchs.com
>     <mailto:sgoldschmidt at de.pepperl-fuchs.com>>
>     >>>>
>     >>>> On socfpga gen5, a warm reboot from Linux currently triggers a warm
>     >>>> reset via reset manager ctrl register.
>     >
>     > is there any reason to not just promote these to cold resets?
> 
>     Why did Altera opt for warm resets on Gen5 in the first place ? I guess
>     to avoid interferring with the FPGA and/or to circumvent problems with
>     board designs which do not connect reset properly (esp. for SPI NOR) ?
> 
> 
> I really don't know. But it's not a question of cold or warm reset. Even
> in warm reset, we could stop to execute spl from sram and always load it
> from flash.

I'd like some answer from Altera/Intel on that :-)

> However, I don't know if this is ok for all users. And this patch only
> fixes the current behaviour of starting it without checking it.

I think it's nice

-- 
Best regards,
Marek Vasut