[U-Boot] [PATCH] arm: zynq: cse_qspi: Fix overwriting spi-rx-bus-width property
Michal Simek
michal.simek at xilinx.com
Wed Nov 21 14:47:48 UTC 2018
From: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>
spi-rx-bus-width property is part of flash, so it should be moved
to flash node from qspi node. This patch fixes the incorrect read
of spi-rx-bus-width property by moving it to flash node.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---
arch/arm/dts/zynq-cse-qspi-single.dts | 2 +-
arch/arm/dts/zynq-cse-qspi.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
index 3252d6a44409..0d680dfc0688 100644
--- a/arch/arm/dts/zynq-cse-qspi-single.dts
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -7,6 +7,6 @@
#include "zynq-cse-qspi.dtsi"
-&qspi {
+&flash0 {
spi-rx-bus-width = <4>;
};
diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi
index 2b169468b06d..65af4081ff4f 100644
--- a/arch/arm/dts/zynq-cse-qspi.dtsi
+++ b/arch/arm/dts/zynq-cse-qspi.dtsi
@@ -59,7 +59,7 @@
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
- flash at 0 {
+ flash0: flash at 0 {
compatible = "n25q128a11";
reg = <0x0>;
spi-tx-bus-width = <1>;
--
1.9.1
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