[U-Boot] Antwort: Re: [PATCH] x86: tsc: Add support for APL soc

[Bernhard Messerklinger]

Hi Bin,

> Missing commit message
I will fix this.
> 
> APL means ApolloLake? Could you please spell it out?
I will fix this.
> 
> > Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger at br-
> automation.com>
> > ---
> >
> >  drivers/timer/tsc_timer.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > index da7c812908..b2a982812a 100644
> > --- a/drivers/timer/tsc_timer.c
> > +++ b/drivers/timer/tsc_timer.c
> > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> >                         80000, 93300, 90000, 88900, 87500 } },
> >         /* Ivybridge */
> >         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > +       /* Intel Atom processor E3900 series */
> > +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> 
> Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> not working for ApolloLake?
I found two ways to get the TSC freq.
1. Read the necessary parameters with cpuid(instruction 15) like it is 
done in 
the kernel.
The problem with this way is that for some reason my core crystal clock is 


always set to zero, so I would need to add the crystal frequency 
somewhere.
2. Read it from MSR.
That?s actually the way I do it in this patch. I only need to add my cpu 
family/model to avoid return with 0 at the begin of cpu_mhz_from_msr.

Please tell me if I overlook something.

Regards,
Bernhard