[U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[Chee, Tien Fong]

On Fri, 2018-11-23 at 13:23 +0100, Marek Vasut wrote:
> On 11/23/2018 10:19 AM, Chee, Tien Fong wrote:
> > 
> > On Wed, 2018-11-21 at 15:11 +0100, Marek Vasut wrote:
> > > 
> > > On 11/21/2018 11:41 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee at intel.com>
> > > > 
> > > > This patch adds description on properties about file name used
> > > > for
> > > > both
> > > > peripheral bitstream and core bitstream.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> > > > ---
> > > >  .../fpga/altera-socfpga-a10-fpga-mgr.txt           |    6
> > > > ++++++
> > > >  1 files changed, 6 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt
> > > > index 2fd8e7a..010322a 100644
> > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > @@ -7,6 +7,10 @@ Required properties:
> > > >                 - The second index is for writing FPGA
> > > > configuration data.
> > > >  - resets     : Phandle and reset specifier for the device's
> > > > reset.
> > > >  - clocks     : Clocks used by the device.
> > > > +- altr,bitstream_periph : File name for FPGA peripheral raw
> > > > binary
> > > > which is used
> > > > +			  to initialize FPGA IOs, PLL, IO48
> > > > and
> > > > DDR.
> > > > +- altr,bitstream_core : File name for core raw binary which
> > > > contains FPGA design
> > > > +			which is used to program FPGA CRAM and
> > > > ERAM.
> > > bitstream- instead of bitstream_
> > Noted.
> > > 
> > > 
> > > btw can we get something that works with full bitstream too ?
> > This patchset actually support the full bitstream too,
> > unfortunately it
> > is blocked by hardware MPFE issue. The patchset for the MPFE
> > workaround
> > would come after this patchset. I would advice to use the early IO
> > release method for the sake of performance.
> > 
> > For details of issue, you can read the from the link https://github
> > .com
> > /altera-opensource/u-boot-
> > socfpga/commits/socfpga_v2014.10_arria10_brin
> > gup
> > FogBugz #410989-6: Masking hardware sequenced warm reset for logic
> > in…  …
> Does that work on ES2 ? I don't think so ...
Why you think it doesn't work, using early IO or full rbf? The
bitstream limitation? What you see from the print out?
>