[U-Boot] [PATCH v4 0/3] RISC-V S-mode support

Anup Patel anup at brainfault.org
Mon Nov 26 10:16:17 UTC 2018


On Mon, Nov 26, 2018 at 2:06 PM Rick Chen <rickchen36 at gmail.com> wrote:
>
> > Hi All,
> >
> >
> >
> > Is it possible to include this series for next U-Boot release?
>
> Hi Anup
>
> Yes.
>
> I will do some verification.
> And prepare the PR ASAP.
>
> Can you prepare a version which will be rebase on the latest u-boot-riscv.git

Sure, give me few minutes.

I will send v5 based on:
commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb
riscv: cache: Implement i/dcache [status, enable, disable]

Regards,
Anup


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