[U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S

[Anup Patel]

On Tue, Nov 27, 2018 at 12:14 PM Rick Chen <rickchen36 at gmail.com> wrote:
>
> > > > > > When we run U-Boot in S-mode the BBL runs from 0x80000000 so this
> > > > > > two lines corrupts BBL instructions.
>
> Hi Anup
>
> You said
> Your patchset based upon git://git.denx.de/u-boot-riscv.git
>
> Why you announce this problem in [PATCH v5 4/4] riscv: Remove
> redundant a2 store on DRAM base in start.S
> Why you do not find this proble in v1, v2, v3, v4 ?

I had this change locally. I thought some would definitely remove this
lines but did not see that happening so I send patch to remove these
lines myself.

Regards,
Anup