[U-Boot] [PATCH] ARM: zynq: Wire SPL configuration for cse nor/nand targets

[Michal Simek]

These symlinks are here only for testing purpose where SPL is used
for soc configuration.

Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 board/xilinx/zynq/zynq-cse-nand | 1 +
 board/xilinx/zynq/zynq-cse-nor  | 1 +
 2 files changed, 2 insertions(+)
 create mode 120000 board/xilinx/zynq/zynq-cse-nand
 create mode 120000 board/xilinx/zynq/zynq-cse-nor

diff --git a/board/xilinx/zynq/zynq-cse-nand b/board/xilinx/zynq/zynq-cse-nand
new file mode 120000
index 000000000000..9d89a9957e03
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nand
@@ -0,0 +1 @@
+zynq-zc770-xm011
\ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-cse-nor b/board/xilinx/zynq/zynq-cse-nor
new file mode 120000
index 000000000000..bb80693eab06
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nor
@@ -0,0 +1 @@
+zynq-zc770-xm012
\ No newline at end of file
-- 
1.9.1