[U-Boot] [RFC PATCH 0/6] SF: Migrate to Linux SPI NOR framework
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Thu Nov 29 11:21:19 UTC 2018
On Thu, Nov 29, 2018 at 11:20 AM Stefan Roese <sr at denx.de> wrote:
>
> On 28.11.18 18:26, Vignesh R wrote:
> > U-Boot SPI NOR support (sf layer) is quite outdated as it does not
> > support 4 byte addressing opcodes, SFDP table and different types of
> > quad mode enable sequences. Many newer flashes no longer support BANK
> > registers use by sf layer to a access >16MB space.
> > Also, many SPI controllers have special MMIO interfaces which provide
> > accelerated read/write access but require knowledge of flash parameters
> > to make use of it. Recent spi-mem layer provides a way to support such
> > flashes but sf layer isnt using that.
> > This patch series syncs SPI NOR framework from Linux v4.19. It also adds
> > spi-mem support on top.
> > So, we gain 4byte addressing support and SFDP support. This makes
> > migrating to U-Boot MTD framework very easy.
> >
> > Tested with few Spansion, micron and macronix flashes with TI's dra7xx,
> > k2g, am43xx EVMs. I dont have access to flashes from other vendors. So,
> > I would greatly appreciate testing on other platforms.
> >
> > This is a RFC, if this approach if fine with the community and get an
> > early feedback. Based on the response, I plan to post
> > official series with better splitting of patches, removing all dead code
> > and fixing up any checkpatch errors.
> >
> > [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig
>
> Thank you very much for working on this. I tested this patchset on
> my MIPS Linkit board with the 4-byte factory strapped Macronix
> mx25l25635e/f. It works like a charm. 4-Byte mode is detected /
> enabled and I can access the complete SPI flash. So please go ahead
> with this patchset. I'll review and test a new patchset version,
> once its ready.
Yes, thanks from here as well. I do think this is the right direction.
I tested this RFC series on socfpga gen5 and it worked with a 32 MiB
Micron chip. But I haven't tested which mode it uses, I'll have to
verify that.
Regards,
Simon
>
> With this, my previous implementation of the 4-byte mode detection
> can be dropped [1].
>
> Thanks,
> Stefan
>
> [1] https://patchwork.ozlabs.org/patch/982525/
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