[U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap()

[Bin Meng]

Hi Lukas,

On Thu, Nov 15, 2018 at 6:59 AM Auer, Lukas
<lukas.auer at aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> > The most significant bit in mcause register should be masked to
> > form the exception code for _exit_trap().
> >
> > Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> > ---
> >
> >  arch/riscv/lib/interrupts.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/lib/interrupts.c
> > b/arch/riscv/lib/interrupts.c
> > index c568706..5e09196 100644
> > --- a/arch/riscv/lib/interrupts.c
> > +++ b/arch/riscv/lib/interrupts.c
> > @@ -73,7 +73,7 @@ ulong handle_trap(ulong mcause, ulong epc, struct
> > pt_regs *regs)
> >       else if ((is_int) && ((mcause & MCAUSE_CAUSE)  == IRQ_M_TIMER))
> >               timer_interrupt(0);     /* handle_m_timer_interrupt
> > */
> >       else
> > -             _exit_trap(mcause, epc, regs);
> > +             _exit_trap(mcause & MCAUSE_CAUSE, epc, regs);
>
> The exception codes differ between traps caused by an interrupt (MSB
> set) and those that are not. Besides software interrupts, the
> handle_trap already checks for all possible machine-mode interrupts.

For the M-mode software interrupts, it will fall into the _exit_trap()
branch which is wrong. Do you mean we just leave it for now until we
support the SBI in the future?

Regards,
Bin