[U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size

[Marty E. Plummer]

On Fri, Sep 14, 2018 at 12:55:19PM +0200, Simon Glass wrote:
> Hi Marty,
> 
> 
> On 13 September 2018 at 23:55, Marty E. Plummer <hanetzer at startmail.com> wrote:
> > Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
> >
> > Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> > is incorrectly detected as 0 Bytes of ram.
> >
> > Signed-off-by: Marty E. Plummer <hanetzer at startmail.com>
> > ---
> >  arch/arm/mach-rockchip/sdram_common.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> > index 650d53e4d9..194dc74b9f 100644
> > --- a/arch/arm/mach-rockchip/sdram_common.c
> > +++ b/arch/arm/mach-rockchip/sdram_common.c
> > @@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> >                       rank, col, bk, cs0_row, bw, row_3_4);
> >         }
> >
> > +       size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
> > +
> 
> Is this because size_mb is only 32-bits?
>
Yeah. This has been discussed a bit before on the ml. 0x1_0000_0000 for
4GiB, and due to memory mapped peripherals it can only address
0xff00_0000 bytes anyways so clamp it down. Code is lifted from
coreboot's init code.
> >         return (size_t)size_mb << 20;
> >  }
> >
> > --
> > 2.18.0
> >
> 
> Regards,
> Simon