[U-Boot] [PATCH v3 2/2] armv7: ls102xa: Disable QE before enter deep sleep

[Ran Wang]

Otherwise system will hang after executing wfi.

Signed-off-by: Ran Wang <ran.wang_1 at nxp.com>
---
Change in v3:
	Actually this is the same to 3/3 patch of v2	

Change in v2:
	None	

 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c         | 4 ++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index af413f8622..bb169aaaf4 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -73,6 +73,7 @@ static void __secure ls1_deepsleep_irq_cfg(void)
 	 * read, that is why we don't read it from register ippdexpcr1 itself.
 	 */
 	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
+	out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
 
 	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
 		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
@@ -192,6 +193,9 @@ static void __secure ls1_deep_sleep(u32 entry_point)
 	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
 	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
 
+	/* Disable QE */
+	setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
+
 	ls1_deepsleep_irq_cfg();
 
 	psci_v7_flush_dcache_all();
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 13a282ffe1..a3d1171aa9 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -86,6 +86,8 @@ struct sys_info {
 	unsigned long freq_localbus;
 };
 
+#define CCSR_DEVDISR1_QE	0x00000001
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
-- 
2.17.1