[U-Boot] [PATCH v2 6/7] riscv: dts: ae350 support SMP

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn at gmail.com> 於 2019年3月29日 週五 下午5:34寫道：
>
> Two more comments regarding ae350_64.dts
>
> On Mon, Mar 25, 2019 at 3:40 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > Cc: Greentime Hu <greentime at andestech.com>
> > ---
> >  arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> >  arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> >  2 files changed, 101 insertions(+), 27 deletions(-)
> >
>
> [snip]
>
> > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> > index e48c298..9e1d63a 100644
> > --- a/arch/riscv/dts/ae350_64.dts
> > +++ b/arch/riscv/dts/ae350_64.dts
> > @@ -26,16 +26,49 @@
> >                         status = "okay";
> >                         compatible = "riscv";
> >                         riscv,isa = "rv64imafdc";
> > +                       riscv,priv-major = <1>;
> > +                       riscv,priv-minor = <10>;
> >                         mmu-type = "riscv,sv39";
> >                         clock-frequency = <60000000>;
> > +                       i-cache-size = <0x8000>;
> > +                       i-cache-line-size = <32>;
> >                         d-cache-size = <0x8000>;
> >                         d-cache-line-size = <32>;
> > +                       next-level-cache = <&L2>;
> >                         CPU0_intc: interrupt-controller {
> >                                 #interrupt-cells = <1>;
> >                                 interrupt-controller;
> >                                 compatible = "riscv,cpu-intc";
> >                         };
> >                 };
> > +               CPU1: cpu at 1 {
> > +                       device_type = "cpu";
> > +                       reg = <1>;
> > +                       status = "okay";
> > +                       compatible = "riscv";
> > +                       riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
>
> isa string not recovered

OK
I will remove it.

>
> > +                       riscv,priv-major = <1>;
> > +                       riscv,priv-minor = <10>;
> > +                       mmu-type = "riscv,sv39";
> > +                       clock-frequency = <60000000>;
> > +                       i-cache-size = <0x8000>;
> > +                       i-cache-line-size = <32>;
> > +                       d-cache-size = <0x8000>;
> > +                       d-cache-line-size = <32>;
> > +                       next-level-cache = <&L2>;
> > +                       CPU1_intc: interrupt-controller {
> > +                               #interrupt-cells = <1>;
> > +                               interrupt-controller;
> > +                               compatible = "riscv,cpu-intc";
> > +                       };
> > +               };
> > +
> > +               L2: l2-cache at e0500000 {
> > +                       compatible = "cache";
> > +                       cache-level = <2>;
> > +                       cache-size = <0x40000>;
> > +                       reg = <0x0 0xe0500000 0x0 0x40000>;
> > +               };
> >         };
> >
> >         memory at 0 {
> > @@ -46,7 +79,7 @@
> >         soc {
> >                 #address-cells = <2>;
> >                 #size-cells = <2>;
> > -               compatible = "andestech,riscv-ae350-soc";
> > +               compatible = "simple-bus";
> >                 ranges;
> >
> >         plic0: interrupt-controller at e4000000 {
> > @@ -56,7 +89,7 @@
> >                 interrupt-controller;
> >                 reg = <0x0 0xe4000000 0x0 0x2000000>;
> >                 riscv,ndev=<71>;
> > -               interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> > +               interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
> >         };
> >
> >         plic1: interrupt-controller at e6400000 {
> > @@ -65,13 +98,13 @@
> >                 #interrupt-cells = <2>;
> >                 interrupt-controller;
> >                 reg = <0x0 0xe6400000 0x0 0x400000>;
> > -               riscv,ndev=<1>;
> > -               interrupts-extended = <&CPU0_intc 3>;
> > +                       riscv,ndev=<2>;
> > +                       interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
> >         };
> >
> >         plmt0 at e6000000 {
> >                 compatible = "riscv,plmt0";
> > -                       interrupts-extended = <&CPU0_intc 7>;
> > +      interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
>
> nits: the alignment looks wrong

OK

Thanks
Rick

>
> >                         reg = <0x0 0xe6000000 0x0 0x100000>;
> >                 };
> >         };
> > @@ -146,6 +179,10 @@
> >                 interrupt-parent = <&plic0>;
> >         };
> >
> > +       pmu {
> > +               compatible = "riscv,base-pmu";
> > +       };
> > +
> >         virtio_mmio at fe007000 {
> >                 interrupts = <0x17 0x4>;
> >                 interrupt-parent = <0x2>;
> > --
>
> Regards,
> Bin