[U-Boot] [PATCH v2 1/2] x86: TunnelCreek: switch P state to the highest freq

[Christian Gmeiner]

Hi Bin,

Am Fr., 15. März 2019 um 09:03 Uhr schrieb Bin Meng <bmeng.cn at gmail.com>:
>
> Hi Christian,
>
> On Wed, Mar 13, 2019 at 5:27 PM Christian Gmeiner
> <christian.gmeiner at gmail.com> wrote:
> >
> > Hi all,
> >
> > Am Mo., 11. März 2019 um 15:41 Uhr schrieb Bin Meng <bmeng.cn at gmail.com>:
> > >
> > > Hi Andy,
> > >
> > > On Wed, Mar 6, 2019 at 7:09 PM Andy Shevchenko
> > > <andriy.shevchenko at linux.intel.com> wrote:
> > > >
> > > > On Thu, Feb 28, 2019 at 11:29:50AM +0800, Bin Meng wrote:
> > > > > On Thu, May 24, 2018 at 12:00 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> > > > > > On Thu, Apr 12, 2018 at 4:07 PM, Christian Gmeiner
> > > > > > <christian.gmeiner at gmail.com> wrote:
> > > >
> > > > > So to me this seems to match my understanding about EIST. If this is
> > > > > true, then I can't explain why Christian's patch is needed since the
> > > > > EIST is disabled on TunnelCreek by default and the processor should
> > > > > already run at the highest performance.
> > > >
> > > > The some internal documents I found suggesting that first what one needs to do
> > > > is to be sure that EIST is enabled / disabled by reading a bit from CPUID.
> > > >
> > >
> > > Correct. This is documented in the public Intel SDM too.
> > >
> > > > (There is no mention of the exact bit, I'm guessing it might be X86_FEATURE_EST)
> > > >
> > > > It also refers to IA32_MISC_ENABLE MSR, i.e. bit 20
> > > > (MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) and bit 16
> > > > (MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT), that firmware can set up
> > > > accordingly.
> > > >
> > > > Hope this helps.
> > > >
> > >
> > > Thanks for the help. But I was looking for clarification on what
> > > frequency the CPU is running at if EIST is disabled (the default
> > > power-up state). Especially I suspect the Intel CPU is running at the
> > > highest frequency when ESIT is disabled hence the highest performance.
> > > Such details are not documented in the public Intel SDM. :(
> > >
> > > > P.S. All names are implying Linux kernel source code.
> > >
> >
> > I think I need to clarify how I came to this patch.
> >
> > Back in the days when we used an Intel BLDK based BIOS solution we did
> > some performance
> > measurements and found out that the same device with an vendor BIOS is
> > much faster. So we started
> > to dig into the issue and used bandwidth to do our measurements. We
> > contacted Intel to get support
> > and after lot of ping-pong mails we got a solution.
> >
> > We need to set these two msr registers to the values they provided to us.
> > These msr register should be described in #29324.
>
> Could you please provide details about these 2 MSR registers? And is
> there any official document from Intel about what is the behavior of
> having EIST disabled?
>

I only got an excerpt of two pages describing these 2 MSR and I am quite sure
I am not allowed to share these. As I wrote these MSR should be documented
in #29324 (which I do not have access to).

> >
> > Bin do you have hardware to reproduce this issue I have and what gets
> > fixed with this patch?
>
> Yes, I have the hardware to test. Is the test case able to run in
> U-Boot? I can have a test.

Boot into linux and run https://zsmith.co/bandwidth.html

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info