[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Andes]

From: Rick Chen <rick at andestech.com>

Changes in v3:
Patch 1
- Rename plic_init() as enable_ipi()
- Remove PLIC_BASE_GET() from enable_ipi()
Patch 2
- Add a space before (PLMT)
Patch 6
- Fix some mis-alignments
- Recovery isa string of CPU1

Changes in v2:
- Drop patch1 and replace by simple-bus driver
- Rename nds_plic as andes_plic
- Move initialize plic to PLIC_BASE_GET() and called automatically
- Rename nds_plmt as andes_plmt
- Recovery dts isa string

Rick Chen (7):
  riscv: Add a SYSCON driver for Andestech's PLIC
  riscv: Add a SYSCON driver for Andestech's PLMT
  riscv: ae350: disable ATCPIT100 timer
  riscv: ax25: Add platform-specific Kconfig options
  riscv: ax25: Andes specific cache shall only support in M-mode
  riscv: dts: ae350 support SMP
  riscv: ae350: enable SMP

 arch/riscv/Kconfig                   |  18 ++++++
 arch/riscv/cpu/ax25/Kconfig          |   7 +++
 arch/riscv/dts/ae350_32.dts          |  81 +++++++++++++++++++-------
 arch/riscv/dts/ae350_64.dts          |  81 +++++++++++++++++++-------
 arch/riscv/include/asm/global_data.h |   6 ++
 arch/riscv/include/asm/syscon.h      |   3 +-
 arch/riscv/lib/Makefile              |   2 +
 arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
 arch/riscv/lib/andes_plmt.c          |  53 +++++++++++++++++
 board/AndesTech/ax25-ae350/Kconfig   |   1 +
 configs/ae350_rv32_defconfig         |   1 -
 configs/ae350_rv64_defconfig         |   1 -
 12 files changed, 317 insertions(+), 47 deletions(-)
 create mode 100644 arch/riscv/lib/andes_plic.c
 create mode 100644 arch/riscv/lib/andes_plmt.c

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2.7.4