[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

[Auer, Lukas]

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick at andestech.com>
> 
> Limit the cache configuration only can be supported in M mode.
> It can not be manipulated in S mode.
> 
> Signed-off-by: Rick Chen <rick at andestech.com>
> Cc: Greentime Hu <greentime at andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>  arch/riscv/cpu/ax25/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>