[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn at gmail.com> 於 2019年4月1日 週一 下午5:01寫道：
>
> Hi Rick,
>
> On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
> > Changes in v3:
> > Patch 1
> > - Rename plic_init() as enable_ipi()
> > - Remove PLIC_BASE_GET() from enable_ipi()
> > Patch 2
> > - Add a space before (PLMT)
> > Patch 6
> > - Fix some mis-alignments
> > - Recovery isa string of CPU1
> >
> > Changes in v2:
> > - Drop patch1 and replace by simple-bus driver
> > - Rename nds_plic as andes_plic
> > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > - Rename nds_plmt as andes_plmt
> > - Recovery dts isa string
> >
> > Rick Chen (7):
> >   riscv: Add a SYSCON driver for Andestech's PLIC
> >   riscv: Add a SYSCON driver for Andestech's PLMT
> >   riscv: ae350: disable ATCPIT100 timer
> >   riscv: ax25: Add platform-specific Kconfig options
> >   riscv: ax25: Andes specific cache shall only support in M-mode
> >   riscv: dts: ae350 support SMP
> >   riscv: ae350: enable SMP
> >
>
> Looks good to me. Are you going to send PR to Tom to include SMP
> series in v2019.04?
>

Thanks for your review.
But there seem have some suggestions from Lukas to be fixed.
After that I will send PR to Tom ASAP.

Thanks
Rick
> Regards,
> Bin