[U-Boot] [PATCH v4 4/6] riscv: ax25: Andes specific cache shall only support in M-mode

Andes uboot at andestech.com
Tue Apr 2 07:56:42 UTC 2019

From: Rick Chen <rick at andestech.com>

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick at andestech.com>
Cc: Greentime Hu <greentime at andestech.com>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Reviewed-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9..6b4b92e 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 	bool "AndeStar V5 families specific cache support"
+	depends on RISCV_MMODE
 	  Provide Andes Technology AndeStar V5 families specific cache support.

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