[U-Boot] [PATCH v2] board: pm9g45: Migrate to CONFIG_DM

Ilko Iliev iliev at ronetix.at
Wed Apr 3 14:50:30 UTC 2019


Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB

Signed-off-by: Ilko Iliev <iliev at ronetix.at>
---
Changes for v2:
	- fix undeclared 'PHYS_SDRAM' in pm9g45.c
	- add missing .dtb

 arch/arm/dts/Makefile         |   2 +
 board/ronetix/pm9g45/pm9g45.c |  10 +-
 configs/pm9g45_defconfig      |  44 +++++++--
 include/configs/pm9g45.h      | 173 ++++++++++++++++++----------------
 4 files changed, 135 insertions(+), 94 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..e148e96455 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -598,6 +598,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
 
 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
 
+dtb-$(CONFIG_TARGET_PM9G45) += at91sam9m10g45ek.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
 	at91sam9g15ek.dtb	\
 	at91sam9g25ek.dtb	\
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 17e520a9e9..c5d28c61e2 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -124,7 +124,7 @@ int board_init(void)
 	/* arch number of AT91SAM9M10G45EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	pm9g45_nand_hw_init();
@@ -139,15 +139,15 @@ int board_init(void)
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
-				PHYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
 
 	return 0;
 }
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 928e446c3f..c3f7e1408d 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -2,27 +2,57 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x73f00000
 CONFIG_TARGET_PM9G45=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="fbcon=rotate:3 console=tty0 console=ttyS0,115200 root=/dev/mtdblock4 mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,1664k(env),2M(linux)ro,-(root) rw rootfstype=jffs2"
-# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
 # CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_JFFS2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
 CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 46b8030894..e34873cea7 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -15,110 +15,119 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
-
-#define CONFIG_MACH_TYPE	MACH_TYPE_PM9G45
-
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-/*
- * Hardware drivers
- */
-#define CONFIG_AT91_GPIO	1
-#define CONFIG_ATMEL_USART	1
-#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
-#define	CONFIG_USART_ID			ATMEL_ID_SYS
-
-#define CONFIG_SYS_USE_NANDFLASH	1
-
-/* LED */
-#define CONFIG_AT91_LED
-#define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
-#define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
-
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE	1
-
-#define CONFIG_JFFS2_CMDLINE		1
-#define CONFIG_JFFS2_NAND		1
-#define CONFIG_JFFS2_DEV		"nand0" /* NAND dev jffs2 lives on */
-#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition */
+#define CONFIG_BOOTP_BOOTFILESIZE
 
 /* SDRAM */
-#define PHYS_SDRAM			0x70000000
-#define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
+#define CONFIG_SYS_SDRAM_BASE           0x70000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(3)
-
+#define CONFIG_SYS_NAND_MASK_CLE		BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD3
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
 #endif
 
 /* Ethernet */
-#define CONFIG_MACB			1
-#define CONFIG_RMII			1
-#define CONFIG_NET_RETRY_COUNT		20
-#define CONFIG_RESET_PHY_R		1
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000 /* _UHP_OHCI_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
-
-/* board specific(not enough SRAM) */
-#define CONFIG_AT91SAM9G45_LCD_BASE	PHYS_SDRAM + 0xE00000
-
-#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM + 0x2000000 /* load addr */
-
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END		CONFIG_AT91SAM9G45_LCD_BASE
-
-/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET		0x60000
-#define CONFIG_ENV_OFFSET_REDUND	0x80000
-#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_NAND_BOOT
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#elif CONFIG_SD_BOOT
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x71000000 dtb; " \
+				"fatload mmc 0:1 0x72000000 zImage; " \
+				"bootz 0x72000000 - 0x71000000"
+#endif
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
-					0x1000)
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					      128 * 1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SD_BOOT
+
+#define CONFIG_SPL_BSS_START_ADDR	0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
-				GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
 
 #endif
-- 
2.17.1



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