[U-Boot] [PATCH v2 1/2] x86: TunnelCreek: switch P state to the highest freq
andriy.shevchenko at linux.intel.com
Thu Apr 4 12:54:00 UTC 2019
On Mon, Apr 01, 2019 at 04:08:33PM +0800, Bin Meng wrote:
> On Mon, Apr 1, 2019 at 3:48 PM Christian Gmeiner
> <christian.gmeiner at gmail.com> wrote:
> > Am Fr., 15. März 2019 um 09:03 Uhr schrieb Bin Meng <bmeng.cn at gmail.com>:
> > > On Wed, Mar 13, 2019 at 5:27 PM Christian Gmeiner
> > > <christian.gmeiner at gmail.com> wrote:
> > > > Am Mo., 11. März 2019 um 15:41 Uhr schrieb Bin Meng <bmeng.cn at gmail.com>:
> > > > > On Wed, Mar 6, 2019 at 7:09 PM Andy Shevchenko
> > > > > <andriy.shevchenko at linux.intel.com> wrote:
> > > > > > On Thu, Feb 28, 2019 at 11:29:50AM +0800, Bin Meng wrote:
> > > > > > > On Thu, May 24, 2018 at 12:00 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> > > > > > > > On Thu, Apr 12, 2018 at 4:07 PM, Christian Gmeiner
> > > > > > > > <christian.gmeiner at gmail.com> wrote:
> > > > We need to set these two msr registers to the values they provided to us.
> > > > These msr register should be described in #29324.
> > >
> > > Could you please provide details about these 2 MSR registers? And is
> > > there any official document from Intel about what is the behavior of
> > > having EIST disabled?
> > >
> > I only got an excerpt of two pages describing these 2 MSR and I am quite sure
> > I am not allowed to share these. As I wrote these MSR should be documented
> > in #29324 (which I do not have access to).
> Thanks for sharing the information.
> Andy, do you have access to the #29324, and check whether it has some
> explanation about my assumption about Intel EIST?
I have no idea what that number means.
Christian might sent me (*) at least a title of the document for easy search.
*) privately to @intel.com address, for example.
With Best Regards,
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