[U-Boot] [EXT] [PATCH v1 2/5] arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
Peng Fan
peng.fan at nxp.com
Mon Apr 8 01:18:20 UTC 2019
> -----Original Message-----
> From: Marcel Ziswiler [mailto:marcel at ziswiler.com]
> Sent: 2019年4月6日 20:47
> To: u-boot at lists.denx.de
> Cc: Marcel Ziswiler <marcel.ziswiler at toradex.com>; Simon Glass
> <sjg at chromium.org>; Peng Fan <peng.fan at nxp.com>; Stefano Babic
> <sbabic at denx.de>; Fabio Estevam <fabio.estevam at nxp.com>; Tom Rini
> <trini at konsulko.com>; Anatolij Gustschin <agust at denx.de>; Albert Aribaud
> <albert.u.boot at aribaud.net>
> Subject: [EXT] [PATCH v1 2/5] arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
>
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>
>
> From: Marcel Ziswiler <marcel.ziswiler at toradex.com>
>
> Add support for lpuart1, lpuart2 and lpuart3.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler at toradex.com>
>
> ---
>
> arch/arm/dts/fsl-imx8dx.dtsi | 54
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index
> 3b1a2a20e3..715abb413d 100644
> --- a/arch/arm/dts/fsl-imx8dx.dtsi
> +++ b/arch/arm/dts/fsl-imx8dx.dtsi
> @@ -236,6 +236,21 @@
> power-domains = <&pd_dma>;
> wakeup-irq = <225>;
> };
> + pd_dma_lpuart1: PD_DMA_UART1 {
> + reg = <SC_R_UART_1>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_dma>;
> + };
> + pd_dma_lpuart2: PD_DMA_UART2 {
> + reg = <SC_R_UART_2>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_dma>;
> + };
> + pd_dma_lpuart3: PD_DMA_UART3 {
> + reg = <SC_R_UART_3>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_dma>;
> + };
> };
> };
>
> @@ -402,6 +417,45 @@
> status = "disabled";
> };
>
> + lpuart1: serial at 5a070000 {
> + compatible = "fsl,imx8qm-lpuart";
> + reg = <0x0 0x5a070000 0x0 0x1000>;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8QXP_UART1_CLK>,
> + <&clk IMX8QXP_UART1_IPG_CLK>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
> + assigned-clock-rates = <80000000>;
> + power-domains = <&pd_dma_lpuart1>;
> + status = "disabled";
> + };
> +
> + lpuart2: serial at 5a080000 {
> + compatible = "fsl,imx8qm-lpuart";
> + reg = <0x0 0x5a080000 0x0 0x1000>;
> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8QXP_UART2_CLK>,
> + <&clk IMX8QXP_UART2_IPG_CLK>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
> + assigned-clock-rates = <80000000>;
> + power-domains = <&pd_dma_lpuart2>;
> + status = "disabled";
> + };
> +
> + lpuart3: serial at 5a090000 {
> + compatible = "fsl,imx8qm-lpuart";
> + reg = <0x0 0x5a090000 0x0 0x1000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8QXP_UART3_CLK>,
> + <&clk IMX8QXP_UART3_IPG_CLK>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
> + assigned-clock-rates = <80000000>;
> + power-domains = <&pd_dma_lpuart3>;
> + status = "disabled";
> + };
> +
> usdhc1: usdhc at 5b010000 {
> compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
> interrupt-parent = <&gic>;
Reviewed-by: Peng Fan <peng.fan at nxp.com>
> --
> 2.20.1
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