[U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

[Parthiban]

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:
> On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
>> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>>  #include <asm/arch/mx6-ddr.h>
>>  #include <asm/arch/mx6-pins.h>
>>  #include <asm/arch/crm_regs.h>
>> +#include <asm/arch/sys_proto.h>
>>  #include <fsl_esdhc.h>
>>  
>>  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 ->
>> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
>>  	MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>  };
>>  
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> +	MX6_PAD_NAND_RE_B__USDHC2_CLK    |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_WE_B__USDHC2_CMD    |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +	MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
> 
> Umm, these pins are already used a few lines up for the NAND, via gpmi:

I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes
either with eMMC or NAND.

> 
>         pinctrl_gpmi_nand: gpminandgrp {
>                 fsl,pins = <
>                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
>                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
>                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
>                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
>                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
>                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
>                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
>                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
>                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
>                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
>                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
>                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
>                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
>                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
>                 >;
>         };
> 
>>  static struct fsl_esdhc_cfg usdhc_cfg[] = {
>>  	{
>>  		.esdhc_base = USDHC1_BASE_ADDR,
>>  		.max_bus_width = 4,
>>  	},
>> +#ifndef CONFIG_NAND_MXS
>> +	{
>> +		.esdhc_base = USDHC2_BASE_ADDR,
>> +		.max_bus_width = 8,
>> +	},
>> +#endif
>>  };
>>  
>>  int board_mmc_getcd(struct mmc *mmc)
>> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>>  
>>  int board_mmc_init(bd_t *bis)
>>  {
>> -	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
>> ARRAY_SIZE(usdhc1_pads));
>> -	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> -
>> -	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
>> +	int i, ret;
>> +
>> +	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> 
> This breaks for the existing phycore_pcl063_defconfig:

Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in
phycore_pcl063_defconfig.

Thanks,
Parthiban N

> 
> board/phytec/pcl063/spl.c: In function ‘board_mmc_init’:
> board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’
> undeclared (first use in this function); did you mean
> ‘CONFIG_SYS_FSL_ESDHC_ADDR’?
>   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>                   ^~~~~~~~~~~~~~~~~~~~~~~~
> 
> 
> Martyn
>