[U-Boot] [V3 1/3] sunxi: Fix A33 memory initialization
jagan at amarulasolutions.com
Tue Apr 9 09:17:29 UTC 2019
On Thu, Mar 28, 2019 at 4:55 PM Jagan Teki <jagan at amarulasolutions.com> wrote:
> On Mon, Mar 18, 2019 at 3:20 PM Shyam Saini
> <shyam.saini at amarulasolutions.com> wrote:
> > From: Michael Trimarchi <michael at amarulasolutions.com>
> > While the exact problem is not known, based on discussion between
> > Philipp Tomsich and André Przywara it is guessed that exit self-refresh
> > timing is not set with correct value. There may be implicit enter or
> > exit Self-Refresh anywhere as part of some training phase.
> > In ZynqMP register guide , which is close to the various
> > Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL
> > tXS is bits [6:0]: Self refresh exit delay. So it could be safely
> > increased and it only affects the time after the self-refresh “exit”,
> > which happens only after (re-)initialisation.
> > There was no document for cpu in question so based on oscilloscope
> > readings  and observed result by comparing allwinner architecture.
> > So set it same as Allwinner H5 silicon.
> > Before this patch, failure rate of was 7%.
> > This was tested on A33 allwinner cpu, dual rank connection connected
> > with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3
> > 1.5V
> >  https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html
> >  https://ibb.co/R70zmyS
> >  https://ibb.co/HVVCGQ8
> > Signed-off-by: Michael Trimarchi <michael at amarulasolutions.com>
> > Signed-off-by: Shyam Saini <shyam.saini at amarulasolutions.com>
> > ---
> > Changelogs:
> > V1->V2: adjust commit message
> > V2->V3: Adjust commit message based on V2 Discussion
> > ---
> Acked-by: Jagan Teki <jagan at openedev.com>
Applied to u-boot-sunxi/master
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