[U-Boot] [PATCH v4 4/4] arm: socfpga: gen5: reduce SPL pre-reloc malloc

Simon Goldschmidt simon.k.r.goldschmidt at gmail.com
Tue Apr 9 19:02:06 UTC 2019

By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>

Changes in v4: None
Changes in v3:
- adapt to socfpga-next

Changes in v2:
- added patch to reduce gen5 SPL initial malloc pool to 2 KiB

 arch/arm/mach-socfpga/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 3c6c63067d..8f7b79f586 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,9 @@ config NR_DRAM_BANKS
 	default 0x00800000 if TARGET_SOCFPGA_GEN5
+	default 0x800 if TARGET_SOCFPGA_GEN5
 	default 0xa2

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