[U-Boot] [PATCH] imx: Add variscite DART-6UL Evaluation Kit
Parthiban Nallathambi
parthitce at gmail.com
Thu Apr 18 09:45:29 UTC 2019
Hello Peng,
On 4/18/19 2:50 AM, Peng Fan wrote:
>
>>
>>
>> Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL
>> iMX6ULL SoM.
>>
>> CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
>> CPU: Commercial temperature grade (0C to 95C) at 43C
>> Reset cause: POR
>> Model: Variscite DART-6UL Evaluation Kit
>> Board: Variscite DART-6UL Evaluation Kit
>> DRAM: 512 MiB
>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>> In: serial at 02020000
>> Out: serial at 02020000
>> Err: serial at 02020000
>> Net: FEC0
>>
>> Working:
>> - Eth0
>> - i2c
>> - MMC/SD
>> - eMMC
>> - USB host
>> - UART 1
>>
>> Note: LCDIF porting needs DM_VIDEO
>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d
>> enx.de%2Fpipermail%2Fu-boot%2F2019-April%2F365506.html&data=02
>> %7C01%7Cpeng.fan%40nxp.com%7Ced2e2a78aa28409c4c1c08d6c380a738
>> %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636911354661076
>> 012&sdata=meF0d06pEsGDBXW83kDMr10Qu%2FafP76xBhdzFCzp8VY%
>> 3D&reserved=0
>>
>> Signed-off-by: Parthiban Nallathambi <parthitce at gmail.com>
>> ---
>> arch/arm/Kconfig | 1 +
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/imx6ull-dart-6ul.dts | 39 ++++
>> arch/arm/dts/imx6ull-dart-6ul.dtsi | 261
>> +++++++++++++++++++++++++++
>> arch/arm/mach-imx/mx6/Kconfig | 12 ++
>> board/variscite/dart_6ul/Kconfig | 12 ++
>> board/variscite/dart_6ul/MAINTAINERS | 8 +
>> board/variscite/dart_6ul/Makefile | 4 +
>> board/variscite/dart_6ul/README | 41 +++++
>> board/variscite/dart_6ul/dart_6ul.c | 228 +++++++++++++++++++++++
>> board/variscite/dart_6ul/spl.c | 215 ++++++++++++++++++++++
>> configs/variscite_dart6ul_defconfig | 55 ++++++
>> include/configs/dart_6ul.h | 131 ++++++++++++++
>> 13 files changed, 1008 insertions(+)
>> create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dts create mode
>> 100644 arch/arm/dts/imx6ull-dart-6ul.dtsi
>> create mode 100644 board/variscite/dart_6ul/Kconfig create mode
>> 100644 board/variscite/dart_6ul/MAINTAINERS
>> create mode 100644 board/variscite/dart_6ul/Makefile create mode
>> 100644 board/variscite/dart_6ul/README create mode 100644
>> board/variscite/dart_6ul/dart_6ul.c
>> create mode 100644 board/variscite/dart_6ul/spl.c create mode 100644
>> configs/variscite_dart6ul_defconfig
>> create mode 100644 include/configs/dart_6ul.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
>> 4640f3b3bd..c20866c86a 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -1635,6 +1635,7 @@ source "board/tcl/sl50/Kconfig"
>> source "board/ucRobotics/bubblegum_96/Kconfig"
>> source "board/birdland/bav335x/Kconfig"
>> source "board/toradex/colibri_pxa270/Kconfig"
>> +source "board/variscite/dart_6ul/Kconfig"
>> source "board/vscom/baltos/Kconfig"
>> source "board/woodburn/Kconfig"
>> source "board/xilinx/Kconfig"
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
>> 0aee8dfde0..6fb545dc9f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -549,6 +549,7 @@ dtb-$(CONFIG_MX6UL) += \
>> dtb-$(CONFIG_MX6ULL) += \
>> imx6ull-14x14-evk.dtb \
>> imx6ull-colibri.dtb \
>> + imx6ull-dart-6ul.dtb
>>
>> dtb-$(CONFIG_ARCH_MX6) += \
>> imx6-colibri.dtb
>> diff --git a/arch/arm/dts/imx6ull-dart-6ul.dts
>> b/arch/arm/dts/imx6ull-dart-6ul.dts
>> new file mode 100644
>> index 0000000000..4cab1a048b
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-dart-6ul.dts
>> @@ -0,0 +1,39 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com> */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx6ull.dtsi"
>> +#include "imx6ull-dart-6ul.dtsi"
>> +
>> +/ {
>> + model = "Variscite DART-6UL Evaluation Kit";
>> + compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull"; };
>> +
>> +&usdhc2 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + srp-disable;
>> + hnp-disable;
>> + adp-disable;
>> + status = "okay";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID
>> 0x17059
>> + >;
>> + };
>> +
>> +};
>> diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi
>> b/arch/arm/dts/imx6ull-dart-6ul.dtsi
>> new file mode 100644
>> index 0000000000..e96669f493
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi
>> @@ -0,0 +1,261 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com> */
>> +
>> +/ {
>> + model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
>> + compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
>> +
>> + memory {
>> + reg = <0x80000000 0x20000000>;
>> + };
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet1>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy0>;
>> + status = "okay";
>> +
>> + mdio1: mdio1 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy at 1 {
>> + reg = <1>;
>> + micrel,led-mode = <1>;
>> + };
>> + };
>> +};
>> +
>> +&fec2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet2>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy1>;
>> + status = "okay";
>> +
>> + mdio2: mdio2 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy1: ethernet-phy at 2 {
>> + reg = <2>;
>> + micrel,led-mode = <1>;
>> + };
>> + };
>> +};
>> +
>> +&gpmi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpmi_nand>;
>> + nand-on-flash-bbt;
>> + fsl,no-blockmark-swap;
>> + status = "disabled";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition at 0 {
>> + label = "uboot";
>> + reg = <0x0 0x400000>;
>> + };
>> +
>> + partition at 400000 {
>> + label = "uboot-env";
>> + reg = <0x400000 0x100000>;
>> + };
>> +
>> + partition at 500000 {
>> + label = "root";
>> + reg = <0x500000 0x0>;
>> + };
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
>> + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
>> + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
>> + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
>> + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +
>> + eeprom at 50 {
>> + compatible = "cat,24c32";
>> + reg = <0x50>;
>> + };
>> +};
>> +
>> +&pwm1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm1>;
>> + #pwm-cells = <3>;
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + bus-width = <0x4>;
>> + no-1-8-v;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + bus-width = <8>;
>> + no-1-8-v;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "disabled";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> +
>> + pinctrl_enet1: enet1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO
>> 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC
>> 0X1b0b0
>> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN
>> 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER
>> 0x1b0b0
>> +
>> MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> +
>> MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN
>> 0x1b0b0
>> +
>> MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> +
>> MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> +
>> MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>> + >;
>> + };
>> +
>> + pinctrl_enet2: enet2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO
>> 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC
>> 0X1b0b0
>> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN
>> 0x1b0b0
>> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER
>> 0x1b0b0
>> +
>> MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
>> +
>> MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN
>> 0x1b0b0
>> +
>> MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
>> +
>> MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
>> +
>> MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>> + >;
>> + };
>> +
>> + pinctrl_gpmi_nand: gpminandgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_DQS__RAWNAND_DQS
>> 0x0b0b1
>> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE
>> 0x0b0b1
>> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE
>> 0x0b0b1
>> +
>> MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
>> +
>> MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>> +
>> MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
>> +
>> MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
>> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B
>> 0x0b0b1
>> +
>> MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
>> +
>> MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2cgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL
>> 0x4001b8b0
>> + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA
>> 0x4001b8b0
>> + >;
>> + };
>> +
>> + pinctrl_i2c1_gpio: i2c1grp_gpio {
>> + fsl,pins = <
>> + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28
>> 0x1b8b0
>> + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29
>> 0x1b8b0
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2cgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL
>> 0x4001b8b0
>> + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA
>> 0x4001b8b0
>> + >;
>> + };
>> +
>> + pinctrl_i2c2_gpio: i2c2grp_gpio {
>> + fsl,pins = <
>> + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30
>> 0x1b8b0
>> + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31
>> 0x1b8b0
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_LCD_DATA00__GPIO3_IO05
>> 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> +
>> MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> +
>> MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD
>> 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK
>> 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0
>> 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1
>> 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2
>> 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3
>> 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19
>> 0x17059
>> +
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD
>> 0x170f9
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK
>> 0x100f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6
>> 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7
>> 0x170f9
>> + >;
>> + };
>> +};
>> diff --git a/arch/arm/mach-imx/mx6/Kconfig
>> b/arch/arm/mach-imx/mx6/Kconfig index e782859b1e..f513c4c06f 100644
>> --- a/arch/arm/mach-imx/mx6/Kconfig
>> +++ b/arch/arm/mach-imx/mx6/Kconfig
>> @@ -161,6 +161,18 @@ config TARGET_COLIBRI_IMX6ULL
>> select DM_THERMAL
>> select MX6ULL
>>
>> +config TARGET_DART_6UL
>> + bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
>> + select MX6ULL
>> + select DM
>> + select DM_ETH
>> + select DM_GPIO
>> + select DM_I2C
>> + select DM_MMC
>> + select DM_SERIAL
>> + select DM_THERMAL
>> + select SUPPORT_SPL
>> +
>> config TARGET_DHCOMIMX6
>> bool "dh_imx6"
>> select BOARD_EARLY_INIT_F
>> diff --git a/board/variscite/dart_6ul/Kconfig
>> b/board/variscite/dart_6ul/Kconfig
>> new file mode 100644
>> index 0000000000..1765af1d82
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/Kconfig
>> @@ -0,0 +1,12 @@
>> +if TARGET_DART_6UL
>> +
>> +config SYS_BOARD
>> + default "dart_6ul"
>> +
>> +config SYS_VENDOR
>> + default "variscite"
>> +
>> +config SYS_CONFIG_NAME
>> + default "dart_6ul"
>> +
>> +endif
>> diff --git a/board/variscite/dart_6ul/MAINTAINERS
>> b/board/variscite/dart_6ul/MAINTAINERS
>> new file mode 100644
>> index 0000000000..339f93fa66
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/MAINTAINERS
>> @@ -0,0 +1,8 @@
>> +MX6UL_DART BOARD
>> +M: Parthiban Nallathambi <parthitce at gmail.com>
>> +S: Maintained
>> +F: arch/arm/dts/imx6ull-dart-6ul.dts
>> +F: arch/arm/dts/imx6ull-dart-6ul.dtsi
>> +F: board/variscite/dart_6ul/
>> +F: configs/variscite_dart6ul_defconfig
>> +F: include/configs/dart_6ul.h
>> diff --git a/board/variscite/dart_6ul/Makefile
>> b/board/variscite/dart_6ul/Makefile
>> new file mode 100644
>> index 0000000000..48aa361bf2
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX-License-Identifier: GPL-2.0+
>> +
>> +obj-y := dart_6ul.o
>> +obj-$(CONFIG_SPL_BUILD) += spl.o
>> diff --git a/board/variscite/dart_6ul/README
>> b/board/variscite/dart_6ul/README new file mode 100644 index
>> 0000000000..d76b997e22
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/README
>> @@ -0,0 +1,41 @@
>> +How to use U-Boot on variscite DART-6UL Evaluation Kit
>> +------------------------------------------------------
>> +
>> +- Configure and build U-Boot for DART-6UL iMX6ULL:
>> +
>> + $ make mrproper
>> + $ make variscite_dart6ul_defconfig
>> + $ make
>> +
>> + This will generate SPL and u-boot-dtb.img images.
>> +
>> +Boot from MMC/SD:
>> +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD
>> card:
>> +
>> + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
>> + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
>> +
>> +- Boot mode settings:
>> +
>> + Boot switch position: SW1 -> 0
>> + SW2 -> 0
>> +
>> +Boot from eMMC:
>> +- if bootpart is not enabled by default, to enable under Linux
>> + echo 0 >/sys/block/mmcblk1boot0/force_ro
>> + mmc bootpart enable 1 1 /dev/mmcblk1boot0
>> +
>> +- Flash the SPL and u-boot-dtb.img to mmcblk1boot0
>> + $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync
>> + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69;
>> +sync
>> +
>> +- Boot mode settings:
>> +
>> + Boot switch position: SW1 -> 0
>> + SW2 -> 1
>> +
>> +- Connect the Serial cable to UART0 and the PC for the console.
>> +
>> +- Insert the micro SD card in the board and power it up.
>> +
>> +- U-Boot messages should come up.
>> diff --git a/board/variscite/dart_6ul/dart_6ul.c
>> b/board/variscite/dart_6ul/dart_6ul.c
>> new file mode 100644
>> index 0000000000..4765595af1
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/dart_6ul.c
>> @@ -0,0 +1,228 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2015-2019 Variscite Ltd.
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com> */
>> +
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <asm/arch/mx6-pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/mach-imx/iomux-v3.h>
>> +#include <asm/mach-imx/mxc_i2c.h>
>> +#include <fsl_esdhc.h>
>> +#include <linux/bitops.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <usb.h>
>> +#include <usb/ehci-ci.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = imx_ddr_size();
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_NAND_MXS
>> +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE |
>> +PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm
>> | PAD_CTL_SPEED_MED | \
>> + PAD_CTL_SRE_FAST) #define GPMI_PAD_CTRL2
>> +(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) static iomux_v3_cfg_t const
>> +nand_pads[] = {
>
> Is it ok to switch to use pinctrl? I have not try drivers/mtd/nand/raw/mxs_nand_dt.c,
> but it will simplify board code if that could be used for your board.
I haven't checked it myself without the definitions in board file.
Thanks, I will check that.
>
>> + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_CLE__RAWNAND_CLE |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_ALE__RAWNAND_ALE |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_RE_B__RAWNAND_RE_B |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_WE_B__RAWNAND_WE_B |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_WP_B__RAWNAND_WP_B |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_READY_B__RAWNAND_READY_B |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>> + MX6_PAD_NAND_DQS__RAWNAND_DQS |
>> MUX_PAD_CTRL(GPMI_PAD_CTRL2), };
>> +
>> +static void setup_gpmi_nand(void)
>> +{
>> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
>> +*)CCM_BASE_ADDR;
>> +
>> + /* config gpmi nand iomux */
>> + imx_iomux_v3_setup_multiple_pads(nand_pads,
>> + ARRAY_SIZE(nand_pads));
>> +
>> + clrbits_le32(&mxc_ccm->CCGR4,
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
>> +
>> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>> +
>> + /*
>> + * config gpmi and bch clock to 100 MHz
>> + * bch/gpmi select PLL2 PFD2 400M
>> + * 100M = 400M / 4
>> + */
>> + clrbits_le32(&mxc_ccm->cscmr1,
>> + MXC_CCM_CSCMR1_BCH_CLK_SEL |
>> + MXC_CCM_CSCMR1_GPMI_CLK_SEL);
>> + clrsetbits_le32(&mxc_ccm->cscdr1,
>> + MXC_CCM_CSCDR1_BCH_PODF_MASK |
>> + MXC_CCM_CSCDR1_GPMI_PODF_MASK,
>> + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
>> |
>> + (3 <<
>> MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
>> +
>> + /* enable gpmi and bch clock gating */
>> + setbits_le32(&mxc_ccm->CCGR4,
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
>> +
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
>> +
>> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>> +
>> + /* enable apbh clock gating */
>> + setbits_le32(&mxc_ccm->CCGR0,
>> MXC_CCM_CCGR0_APBHDMA_MASK); }
>> +#endif
>> +
>> +#ifdef CONFIG_FEC_MXC
>> +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm |
>> PAD_CTL_SRE_FAST)
>> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE
>> | \
>> + PAD_CTL_SPEED_HIGH |
>> PAD_CTL_DSE_48ohm | \
>> + PAD_CTL_SRE_FAST)
>> +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE
>> | \
>> + PAD_CTL_DSE_48ohm |
>> PAD_CTL_SRE_FAST | \
>> + PAD_CTL_ODE)
>> +/*
>> + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
>> + * be used for ENET1 or ENET2, cannot be used for both.
>> + */
>> +static iomux_v3_cfg_t const fec1_pads[] = {
>
> How about use DM_ETH?
DM_ETH is enabled, but I will adapt with static pad definitions here in
board file.
Thanks,
Parthiban N
>
> Regards,
> Peng.
>
>> + MX6_PAD_GPIO1_IO06__ENET1_MDIO |
>> MUX_PAD_CTRL(MDIO_PAD_CTRL),
>> + MX6_PAD_GPIO1_IO07__ENET1_MDC |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
>> MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>> + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const fec2_pads[] = {
>> + MX6_PAD_GPIO1_IO06__ENET2_MDIO |
>> MUX_PAD_CTRL(MDIO_PAD_CTRL),
>> + MX6_PAD_GPIO1_IO07__ENET2_MDC |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
>> MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>> + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN |
>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_fec(int fec_id) {
>> + if (fec_id == 0)
>> + imx_iomux_v3_setup_multiple_pads(fec1_pads,
>> +
>> ARRAY_SIZE(fec1_pads));
>> + else
>> + imx_iomux_v3_setup_multiple_pads(fec2_pads,
>> +
>> ARRAY_SIZE(fec2_pads));
>> +}
>> +
>> +int board_eth_init(bd_t *bis)
>> +{
>> + int ret = 0;
>> +
>> + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
>> + CONFIG_FEC_MXC_PHYADDR,
>> + IMX_FEC_BASE);
>> +
>> +#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
>> + /* USB Ethernet Gadget */
>> + usb_eth_initialize(bis);
>> +#endif
>> + return ret;
>> +}
>> +
>> +static int setup_fec(int fec_id)
>> +{
>> + struct iomuxc *const iomuxc_regs = (struct iomuxc
>> *)IOMUXC_BASE_ADDR;
>> + int ret;
>> +
>> + if (fec_id == 0) {
>> + /*
>> + * Use 50M anatop loopback REF_CLK1 for ENET1,
>> + * clear gpr1[13], set gpr1[17].
>> + */
>> + clrsetbits_le32(&iomuxc_regs->gpr[1],
>> IOMUX_GPR1_FEC1_MASK,
>> +
>> IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
>> + } else {
>> + /*
>> + * Use 50M anatop loopback REF_CLK2 for ENET2,
>> + * clear gpr1[14], set gpr1[18].
>> + */
>> + clrsetbits_le32(&iomuxc_regs->gpr[1],
>> IOMUX_GPR1_FEC2_MASK,
>> +
>> IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>> + }
>> +
>> + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
>> + if (ret)
>> + return ret;
>> +
>> + enable_enet_clk(1);
>> +
>> + return 0;
>> +}
>> +
>> +int board_phy_config(struct phy_device *phydev) {
>> + /*
>> + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) &
>> select
>> + * 50 MHz RMII clock mode.
>> + */
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
>> +
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> +
>> + return 0;
>> +}
>> +#endif /* CONFIG_FEC_MXC */
>> +
>> +int board_early_init_f(void)
>> +{
>> + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + /* Address of boot parameters */
>> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>> +
>> +#ifdef CONFIG_FEC_MXC
>> + setup_fec(CONFIG_FEC_ENET_DEV);
>> +#endif
>> +
>> +#ifdef CONFIG_NAND_MXS
>> + setup_gpmi_nand();
>> +#endif
>> + return 0;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + puts("Board: Variscite DART-6UL Evaluation Kit\n");
>> +
>> + return 0;
>> +}
>> diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
>> new file mode 100644 index 0000000000..f7e6ab6325
>> --- /dev/null
>> +++ b/board/variscite/dart_6ul/spl.c
>> @@ -0,0 +1,215 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2015-2019 Variscite Ltd.
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com> */
>> +
>> +#include <common.h>
>> +#include <spl.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/mx6-ddr.h>
>> +#include <asm/arch/mx6-pins.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <fsl_esdhc.h>
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |
>> \
>> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |
>> \
>> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +
>> +static iomux_v3_cfg_t const uart1_pads[] = {
>> + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX |
>> MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX |
>> +MUX_PAD_CTRL(UART_PAD_CTRL), };
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(uart1_pads,
>> +ARRAY_SIZE(uart1_pads)); }
>> +
>> +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
>> + .grp_addds = 0x00000030,
>> + .grp_ddrmode_ctl = 0x00020000,
>> + .grp_b0ds = 0x00000030,
>> + .grp_ctlds = 0x00000030,
>> + .grp_b1ds = 0x00000030,
>> + .grp_ddrpke = 0x00000000,
>> + .grp_ddrmode = 0x00020000,
>> + .grp_ddr_type = 0x000c0000,
>> +};
>> +
>> +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
>> + .dram_dqm0 = 0x00000030,
>> + .dram_dqm1 = 0x00000030,
>> + .dram_ras = 0x00000030,
>> + .dram_cas = 0x00000030,
>> + .dram_odt0 = 0x00000030,
>> + .dram_odt1 = 0x00000030,
>> + .dram_sdba2 = 0x00000000,
>> + .dram_sdclk_0 = 0x00000008,
>> + .dram_sdqs0 = 0x00000038,
>> + .dram_sdqs1 = 0x00000030,
>> + .dram_reset = 0x00000030,
>> +};
>> +
>> +static struct mx6_mmdc_calibration mx6_mmcd_calib = {
>> + .p0_mpwldectrl0 = 0x00000000,
>> + .p0_mpdgctrl0 = 0x414C0158,
>> + .p0_mprddlctl = 0x40403A3A,
>> + .p0_mpwrdlctl = 0x40405A56,
>> +};
>> +
>> +struct mx6_ddr_sysinfo ddr_sysinfo = {
>> + .dsize = 0,
>> + .cs_density = 20,
>> + .ncs = 1,
>> + .cs1_mirror = 0,
>> + .rtt_wr = 2,
>> + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
>> + .walat = 1, /* Write additional latency */
>> + .ralat = 5, /* Read additional latency */
>> + .mif3_mode = 3, /* Command prediction working mode
>> */
>> + .bi_on = 1, /* Bank interleaving enabled */
>> + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
>> + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
>> +};
>> +
>> +static struct mx6_ddr3_cfg mem_ddr = {
>> + .mem_speed = 800,
>> + .density = 4,
>> + .width = 16,
>> + .banks = 8,
>> + .rowaddr = 15,
>> + .coladdr = 10,
>> + .pagesz = 2,
>> + .trcd = 1375,
>> + .trcmin = 4875,
>> + .trasmin = 3500,
>> +};
>> +
>> +static void ccgr_init(void)
>> +{
>> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg
>> *)CCM_BASE_ADDR;
>> +
>> + writel(0xFFFFFFFF, &ccm->CCGR0);
>> + writel(0xFFFFFFFF, &ccm->CCGR1);
>> + writel(0xFFFFFFFF, &ccm->CCGR2);
>> + writel(0xFFFFFFFF, &ccm->CCGR3);
>> + writel(0xFFFFFFFF, &ccm->CCGR4);
>> + writel(0xFFFFFFFF, &ccm->CCGR5);
>> + writel(0xFFFFFFFF, &ccm->CCGR6);
>> + writel(0xFFFFFFFF, &ccm->CCGR7);
>> + /* Enable Audio Clock for SOM codec */
>> + writel(0x01130100, (long *)CCM_CCOSR); }
>> +
>> +static void spl_dram_init(void)
>> +{
>> + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs,
>> &mx6_grp_ioregs);
>> + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); }
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW |
>> \
>> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
>> + MX6_PAD_SD1_CLK__USDHC1_CLK |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_CMD__USDHC1_CMD |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DATA0__USDHC1_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DATA1__USDHC1_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DATA2__USDHC1_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DATA3__USDHC1_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> + MX6_PAD_NAND_RE_B__USDHC2_CLK |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_WE_B__USDHC2_CMD |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
>> +MUX_PAD_CTRL(USDHC_PAD_CTRL), }; #endif
>> +
>> +static struct fsl_esdhc_cfg usdhc_cfg[] = {
>> + {
>> + .esdhc_base = USDHC1_BASE_ADDR,
>> + .max_bus_width = 4,
>> + },
>> +#ifndef CONFIG_NAND_MXS
>> + {
>> + .esdhc_base = USDHC2_BASE_ADDR,
>> + .max_bus_width = 8,
>> + },
>> +#endif
>> +};
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + return 1;
>> +}
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + int i, ret;
>> +
>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> + switch (i) {
>> + case 0:
>> + SETUP_IOMUX_PADS(usdhc1_pads);
>> + usdhc_cfg[i].sdhc_clk =
>> mxc_get_clock(MXC_ESDHC_CLK);
>> + break;
>> +#ifndef CONFIG_NAND_MXS
>> + case 1:
>> + SETUP_IOMUX_PADS(usdhc2_pads);
>> + usdhc_cfg[i].sdhc_clk =
>> mxc_get_clock(MXC_ESDHC2_CLK);
>> + break;
>> +#endif
>> + default:
>> + printf("Warning - USDHC%d controller not
>> supporting\n",
>> + i + 1);
>> + return 0;
>> + }
>> +
>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> + if (ret) {
>> + printf("Warning: failed to initialize mmc
>> dev %d\n", i);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> + /* setup AIPS and disable watchdog */
>> + arch_cpu_init();
>> +
>> + ccgr_init();
>> +
>> + /* setup GP timer */
>> + timer_init();
>> +
>> + setup_iomux_uart();
>> +
>> + /* iomux and setup of i2c */
>> + board_early_init_f();
>> +
>> + /* UART clocks enabled and gd valid - init serial console */
>> + preloader_console_init();
>> +
>> + /* DDR initialization */
>> + spl_dram_init();
>> +
>> + /* Clear the BSS. */
>> + memset(__bss_start, 0, __bss_end - __bss_start);
>> +
>> + /* load/boot image from boot device */
>> + board_init_r(NULL, 0);
>> +}
>> diff --git a/configs/variscite_dart6ul_defconfig
>> b/configs/variscite_dart6ul_defconfig
>> new file mode 100644
>> index 0000000000..a1cdd05619
>> --- /dev/null
>> +++ b/configs/variscite_dart6ul_defconfig
>> @@ -0,0 +1,55 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_MX6=y
>> +CONFIG_SYS_TEXT_BASE=0x86000000
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_TARGET_DART_6UL=y
>> +CONFIG_SPL_MMC_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_SPL=y
>> +# CONFIG_CMD_DEKBLOB is not set
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_NR_DRAM_BANKS=8
>> +CONFIG_FIT=y
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.
>> cfg"
>> +CONFIG_BOOTDELAY=3
>> +# CONFIG_USE_BOOTCOMMAND is not set
>> +CONFIG_BOARD_EARLY_INIT_F=y
>> +CONFIG_SPL_USB_HOST_SUPPORT=y
>> +CONFIG_SPL_WATCHDOG_SUPPORT=y
>> +CONFIG_CMD_DM=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +# CONFIG_RANDOM_UUID is not set
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_USB_SDP=y
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_CMD_NET=y
>> +# CONFIG_ISO_PARTITION is not set
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
>> +CONFIG_DM_I2C_GPIO=y
>> +CONFIG_SYS_I2C_MXC=y
>> +CONFIG_FSL_ESDHC=y
>> +CONFIG_PHYLIB=y
>> +CONFIG_PHY_MICREL=y
>> +CONFIG_FEC_MXC=y
>> +CONFIG_MII=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_PINCTRL_IMX6=y
>> +CONFIG_DM_PMIC=y
>> +# CONFIG_SPL_PMIC_CHILDREN is not set
>> +CONFIG_DM_REGULATOR=y
>> +CONFIG_DM_REGULATOR_FIXED=y
>> +CONFIG_MXC_UART=y
>> +CONFIG_USB=y
>> +CONFIG_DM_USB=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_USB_GADGET_MANUFACTURER="Variscite"
>> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>> +CONFIG_CI_UDC=y
>> +CONFIG_USB_GADGET_DOWNLOAD=y
>> +CONFIG_LZO=y
>> diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h new file
>> mode 100644 index 0000000000..fb1b899d71
>> --- /dev/null
>> +++ b/include/configs/dart_6ul.h
>> @@ -0,0 +1,131 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Board configuration file for Variscite DART-6UL Evaluation Kit
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com> */
>> +#ifndef __DART_6UL_H #define __DART_6UL_H
>> +
>> +#include <linux/sizes.h>
>> +#include "mx6_common.h"
>> +
>> +/* SPL options */
>> +#include "imx6_spl.h"
>> +
>> +/* NAND pin conflicts with usdhc2 */
>> +#ifdef CONFIG_CMD_NAND
>> +#define CONFIG_SYS_FSL_USDHC_NUM 1
>> +#else
>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>> +#endif
>> +
>> +#ifdef CONFIG_CMD_NET
>> +#define CONFIG_FEC_ENET_DEV 0
>> +
>> +#if (CONFIG_FEC_ENET_DEV == 0)
>> +#define IMX_FEC_BASE ENET_BASE_ADDR
>> +#define CONFIG_FEC_MXC_PHYADDR 0x1
>> +#define CONFIG_FEC_XCV_TYPE RMII
>> +#define CONFIG_ETHPRIME "eth0"
>> +#elif (CONFIG_FEC_ENET_DEV == 1)
>> +#define IMX_FEC_BASE ENET2_BASE_ADDR
>> +#define CONFIG_FEC_MXC_PHYADDR 0x3
>> +#define CONFIG_FEC_XCV_TYPE RMII
>> +#define CONFIG_ETHPRIME "eth1"
>> +#endif
>> +#endif
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
>> +
>> +/* Environment settings */
>> +#define CONFIG_ENV_SIZE SZ_8K
>> +#define CONFIG_ENV_OFFSET (14 * SZ_64K)
>> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
>> +#define CONFIG_ENV_OFFSET_REDUND \
>> + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
>> +
>> +/* Environment in SD */
>> +#define CONFIG_SYS_MMC_ENV_DEV 0
>> +#define CONFIG_SYS_MMC_ENV_PART 0
>> +#define MMC_ROOTFS_DEV 0
>> +#define MMC_ROOTFS_PART 2
>> +
>> +/* Console configs */
>> +#define CONFIG_MXC_UART_BASE UART1_BASE
>> +
>> +/* MMC Configs */
>> +#define CONFIG_FSL_USDHC
>> +
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
>> +#define CONFIG_SUPPORT_EMMC_BOOT
>> +
>> +/* I2C configs */
>> +#ifdef CONFIG_CMD_I2C
>> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1
>> */
>> +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2
>> */
>> +#define CONFIG_SYS_I2C_SPEED 100000
>> +#endif
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_MEMTEST_START 0x80000000
>> +#define CONFIG_SYS_MEMTEST_END
>> (CONFIG_SYS_MEMTEST_START + 0x8000000)
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +/* Physical Memory Map */
>> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>> +#define PHYS_SDRAM_SIZE SZ_512M
>> +
>> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> #define
>> +CONFIG_SYS_INIT_SP_ADDR \
>> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* USB Configs */
>> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI |
>> PORT_PTS_PTW)
>> +#define CONFIG_MXC_USB_FLAGS 0
>> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>> +
>> +#define CONFIG_IMX_THERMAL
>> +
>> +#define ENV_MMC \
>> + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
>> + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
>> + "fitpart=1\0" \
>> + "bootdelay=3\0" \
>> + "silent=1\0" \
>> + "optargs=rw rootwait\0" \
>> + "mmcautodetect=yes\0" \
>> + "mmcrootfstype=ext4\0" \
>> + "mmcfit_name=fitImage\0" \
>> + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
>> + "${mmcfit_name}\0" \
>> + "mmcargs=setenv bootargs " \
>> + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} "
>> \
>> + "console=${console} rootfstype=${mmcrootfstype}\0" \
>> + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm
>> +${fit_addr}\0" \
>> +
>> +/* Default environment */
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "fdt_high=0xffffffff\0" \
>> + "console=ttymxc0,115200n8\0" \
>> + "addcon=setenv bootargs ${bootargs}
>> console=${console},${baudrate}\0" \
>> + "fit_addr=0x82000000\0" \
>> + ENV_MMC
>> +
>> +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
>> +
>> +#define BOOT_TARGET_DEVICES(func) \
>> + func(MMC, mmc, 0) \
>> + func(MMC, mmc, 1) \
>> + func(DHCP, dhcp, na)
>> +
>> +#include <config_distro_bootcmd.h>
>> +#endif /* __DART_6UL_H */
>> --
>> 2.17.2
>
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