[U-Boot] [PATCH v2] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM
Parthiban Nallathambi
parthitce at gmail.com
Fri Apr 26 08:02:35 UTC 2019
Ping on this patch.
Thanks,
Parthiban N
On 4/10/19 4:35 PM, Parthiban Nallathambi wrote:
> Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
> with eMMC on SoM.
>
> CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
> CPU: Industrial temperature grade (-40C to 105C) at 38C
> Reset cause: POR
> Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
> Board: PHYTEC phyCORE-i.MX6ULL
> DRAM: 256 MiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> In: serial at 02020000
> Out: serial at 02020000
> Err: serial at 02020000
> Net: FEC0
>
> Working:
> - Eth0
> - i2C
> - MMC/SD
> - eMMC
> - UART (1 & 5)
> - USB (host & otg)
>
> Signed-off-by: Parthiban Nallathambi <parthitce at gmail.com>
> ---
>
> Notes:
> Changes in v2:
> - disabled gpmi and usdhc by default in pcl063-common.dtsi. Board
> dts enables it based on the flash storage which is present.
> - added CONFIG_SYS_FSL_USDHC_NUM in pcl063.h
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/imx6ul-phycore-segin.dts | 7 +-
> arch/arm/dts/imx6ull-phycore-segin.dts | 70 +++++++++++
> ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} | 33 ++++-
> arch/arm/mach-imx/mx6/Kconfig | 12 ++
> board/phytec/pcl063/Kconfig | 13 ++
> board/phytec/pcl063/MAINTAINERS | 6 +-
> board/phytec/pcl063/pcl063.c | 5 +-
> board/phytec/pcl063/spl.c | 76 +++++++++++-
> configs/phycore_pcl063_ull_defconfig | 54 ++++++++
> include/configs/pcl063.h | 2 +
> include/configs/pcl063_ull.h | 117 ++++++++++++++++++
> 12 files changed, 384 insertions(+), 12 deletions(-)
> create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
> rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (83%)
> create mode 100644 configs/phycore_pcl063_ull_defconfig
> create mode 100644 include/configs/pcl063_ull.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 930b7e03db..8459acb344 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
> dtb-$(CONFIG_MX6ULL) += \
> imx6ull-14x14-evk.dtb \
> imx6ull-colibri.dtb \
> + imx6ull-phycore-segin.dtb
>
> dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> imx7d-sdb-qspi.dtb \
> diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts
> index a46012e2b4..7d68bf8430 100644
> --- a/arch/arm/dts/imx6ul-phycore-segin.dts
> +++ b/arch/arm/dts/imx6ul-phycore-segin.dts
> @@ -16,7 +16,8 @@
>
> /dts-v1/;
>
> -#include "imx6ul-pcl063.dtsi"
> +#include "imx6ul.dtsi"
> +#include "pcl063-common.dtsi"
>
> / {
> model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
> @@ -24,6 +25,10 @@
> "fsl,imx6ul";
> };
>
> +&gpmi {
> + status = "okay";
> +};
> +
> &i2c1 {
> i2c_rtc: rtc at 68 {
> compatible = "microcrystal,rv4162";
> diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts b/arch/arm/dts/imx6ull-phycore-segin.dts
> new file mode 100644
> index 0000000000..6df3ad2e4a
> --- /dev/null
> +++ b/arch/arm/dts/imx6ull-phycore-segin.dts
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ull.dtsi"
> +#include "pcl063-common.dtsi"
> +
> +/ {
> + model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
> + compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
> + "fsl,imx6ull";
> +};
> +
> +&i2c1 {
> + i2c_rtc: rtc at 68 {
> + compatible = "microcrystal,rv4162";
> + reg = <0x68>;
> + status = "okay";
> + };
> +};
> +
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
> + dr_mode = "otg";
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
> + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
> + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usb_otg1_id: usbotg1idgrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
> + >;
> + };
> +
> +};
> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/pcl063-common.dtsi
> similarity index 83%
> rename from arch/arm/dts/imx6ul-pcl063.dtsi
> rename to arch/arm/dts/pcl063-common.dtsi
> index 24a6a47983..2b14b2dc5f 100644
> --- a/arch/arm/dts/imx6ul-pcl063.dtsi
> +++ b/arch/arm/dts/pcl063-common.dtsi
> @@ -7,10 +7,6 @@
> * Author: Christian Hemp <c.hemp at phytec.de>
> */
>
> -/dts-v1/;
> -
> -#include "imx6ul.dtsi"
> -
> / {
> model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
> compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
> @@ -47,7 +43,7 @@
> pinctrl-0 = <&pinctrl_gpmi_nand>;
> nand-on-flash-bbt;
> fsl,no-blockmark-swap;
> - status = "okay";
> + status = "disabled";
>
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -99,6 +95,18 @@
> status = "okay";
> };
>
> +&usdhc2 {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> + keep-power-in-suspend;
> + status = "disabled";
> +};
> +
> &iomuxc {
> pinctrl-names = "default";
>
> @@ -170,4 +178,19 @@
>
> >;
> };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
> + >;
> + };
> };
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index e782859b1e..5e2f08e500 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -443,6 +443,18 @@ config TARGET_PCL063
> select DM_THERMAL
> select SUPPORT_SPL
>
> +config TARGET_PCL063_ULL
> + bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
> + select MX6ULL
> + select DM
> + select DM_ETH
> + select DM_GPIO
> + select DM_I2C
> + select DM_MMC
> + select DM_SERIAL
> + select DM_THERMAL
> + select SUPPORT_SPL
> +
> config TARGET_SECOMX6
> bool "secomx6 boards"
>
> diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig
> index 977db70f64..58f72f2791 100644
> --- a/board/phytec/pcl063/Kconfig
> +++ b/board/phytec/pcl063/Kconfig
> @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
> default "pcl063"
>
> endif
> +
> +if TARGET_PCL063_ULL
> +
> +config SYS_BOARD
> + default "pcl063"
> +
> +config SYS_VENDOR
> + default "phytec"
> +
> +config SYS_CONFIG_NAME
> + default "pcl063_ull"
> +
> +endif
> diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS
> index c65a951f3d..70e03cfe71 100644
> --- a/board/phytec/pcl063/MAINTAINERS
> +++ b/board/phytec/pcl063/MAINTAINERS
> @@ -1,8 +1,12 @@
> PCL063 BOARD
> M: Martyn Welch <martyn.welch at collabora.com>
> +M: Parthiban Nallathambi <parthitce at gmail.com>
> S: Maintained
> -F: arch/arm/dts/imx6ul-pcl063.dtsi
> F: arch/arm/dts/imx6ul-phycore-segin.dts
> +F: arch/arm/dts/imx6ull-phycore-segin.dts
> +F: arch/arm/dts/pcl063-common.dtsi
> F: board/phytec/pcl063/
> F: configs/phycore_pcl063_defconfig
> +F: configs/phycore_pcl063_ull_defconfig
> F: include/configs/pcl063.h
> +F: include/configs/pcl063_ull.h
> diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
> index 38b233d1b0..17012df037 100644
> --- a/board/phytec/pcl063/pcl063.c
> +++ b/board/phytec/pcl063/pcl063.c
> @@ -200,7 +200,10 @@ int board_init(void)
>
> int checkboard(void)
> {
> - puts("Board: PHYTEC phyCORE-i.MX6UL\n");
> + u32 cpurev = get_cpu_rev();
> +
> + printf("Board: PHYTEC phyCORE-i.MX%s\n",
> + get_imx_type((cpurev & 0xFF000) >> 12));
>
> return 0;
> }
> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
> index b93cd493f2..73a774645d 100644
> --- a/board/phytec/pcl063/spl.c
> +++ b/board/phytec/pcl063/spl.c
> @@ -13,6 +13,7 @@
> #include <asm/arch/mx6-ddr.h>
> #include <asm/arch/mx6-pins.h>
> #include <asm/arch/crm_regs.h>
> +#include <asm/arch/sys_proto.h>
> #include <fsl_esdhc.h>
>
> /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
> MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> };
>
> +#ifndef CONFIG_NAND_MXS
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +#endif
> +
> static struct fsl_esdhc_cfg usdhc_cfg[] = {
> {
> .esdhc_base = USDHC1_BASE_ADDR,
> .max_bus_width = 4,
> },
> +#ifndef CONFIG_NAND_MXS
> + {
> + .esdhc_base = USDHC2_BASE_ADDR,
> + .max_bus_width = 8,
> + },
> +#endif
> };
>
> int board_mmc_getcd(struct mmc *mmc)
> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>
> int board_mmc_init(bd_t *bis)
> {
> - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> -
> - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> + int i, ret;
> +
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + SETUP_IOMUX_PADS(usdhc1_pads);
> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + break;
> +#ifndef CONFIG_NAND_MXS
> + case 1:
> + SETUP_IOMUX_PADS(usdhc2_pads);
> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + break;
> +#endif
> + default:
> + printf("Warning - USDHC%d controller not supporting\n",
> + i + 1);
> + return 0;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret) {
> + printf("Warning: failed to initialize mmc dev %d\n", i);
> + return ret;
> + }
> + }
> +
> + return 0;
> }
>
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u32 bmode = imx6_src_get_boot_mode();
> + u8 boot_dev = BOOT_DEVICE_MMC1;
> +
> + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
> + case IMX6_BMODE_SD:
> + case IMX6_BMODE_ESD:
> + boot_dev = BOOT_DEVICE_MMC1;
> + break;
> + case IMX6_BMODE_MMC:
> + case IMX6_BMODE_EMMC:
> + boot_dev = BOOT_DEVICE_MMC2;
> + break;
> + default:
> + /* Default - BOOT_DEVICE_MMC1 */
> + printf("Wrong board boot order\n");
> + break;
> + }
> +
> + spl_boot_list[0] = boot_dev;
> +}
> #endif /* CONFIG_FSL_ESDHC */
>
> void board_init_f(ulong dummy)
> diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
> new file mode 100644
> index 0000000000..75408a8344
> --- /dev/null
> +++ b/configs/phycore_pcl063_ull_defconfig
> @@ -0,0 +1,54 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_SYS_TEXT_BASE=0x87800000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_TARGET_PCL063_ULL=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +# CONFIG_CMD_DEKBLOB is not set
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=8
> +CONFIG_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> +CONFIG_BOOTDELAY=3
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL_USB_HOST_SUPPORT=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +# CONFIG_RANDOM_UUID is not set
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_SDP=y
> +CONFIG_CMD_CACHE=y
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
> +CONFIG_DM_I2C_GPIO=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX6=y
> +CONFIG_DM_PMIC=y
> +# CONFIG_SPL_PMIC_CHILDREN is not set
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_MXC_UART=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="Phytec"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
> +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
> +CONFIG_CI_UDC=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_LZO=y
> diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
> index 4ceab519cb..c032f05fc5 100644
> --- a/include/configs/pcl063.h
> +++ b/include/configs/pcl063.h
> @@ -24,6 +24,8 @@
> #undef CONFIG_SPL_TEXT_BASE
> #define CONFIG_SPL_TEXT_BASE 0x00909000
>
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +
> /* Size of malloc() pool */
> #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
>
> diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
> new file mode 100644
> index 0000000000..0f1a010b4e
> --- /dev/null
> +++ b/include/configs/pcl063_ull.h
> @@ -0,0 +1,117 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC
> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com>
> + *
> + * Based on include/configs/xpress.h:
> + * Copyright (C) 2015-2016 Stefan Roese <sr at denx.de>
> + */
> +#ifndef __PCL063_ULL_H
> +#define __PCL063_ULL_H
> +
> +#include <linux/sizes.h>
> +#include "mx6_common.h"
> +
> +/* SPL options */
> +#include "imx6_spl.h"
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
> +
> +/* Environment settings */
> +#define CONFIG_ENV_SIZE (0x4000)
> +#define CONFIG_ENV_OFFSET (0x80000)
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +#define CONFIG_ENV_OFFSET_REDUND \
> + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
> +
> +/* Environment in SD */
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +#define CONFIG_SYS_MMC_ENV_PART 0
> +#define MMC_ROOTFS_DEV 0
> +#define MMC_ROOTFS_PART 2
> +
> +/* Console configs */
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
> +#define CONFIG_SUPPORT_EMMC_BOOT
> +
> +/* I2C configs */
> +#ifdef CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#endif
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_MEMTEST_START 0x80000000
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ 1000
> +
> +/* Physical Memory Map */
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +#define PHYS_SDRAM_SIZE SZ_256M
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* NAND */
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +
> +/* USB Configs */
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
> +
> +#define CONFIG_IMX_THERMAL
> +
> +#define ENV_MMC \
> + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
> + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
> + "fitpart=1\0" \
> + "bootdelay=3\0" \
> + "silent=1\0" \
> + "optargs=rw rootwait\0" \
> + "mmcautodetect=yes\0" \
> + "mmcrootfstype=ext4\0" \
> + "mmcfit_name=fitImage\0" \
> + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
> + "${mmcfit_name}\0" \
> + "mmcargs=setenv bootargs " \
> + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
> + "console=${console} rootfstype=${mmcrootfstype}\0" \
> + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
> +
> +/* Default environment */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0xffffffff\0" \
> + "console=ttymxc0,115200n8\0" \
> + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
> + "fit_addr=0x82000000\0" \
> + ENV_MMC
> +
> +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0) \
> + func(MMC, mmc, 1) \
> + func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#endif /* __PCL063_ULL_H */
>
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