[U-Boot] [PATCH v2 2/6] arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error

[Keerthy]

From: Brad Griffis <bgriffis at ti.com>

Add 1ms delay to avoid L3 timeout error during suspend resume.

Signed-off-by: Brad Griffis <bgriffis at ti.com>
Signed-off-by: Keerthy <j-keerthy at ti.com>
---
 arch/arm/mach-omap2/am33xx/ddr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 816d4e8e05..5d947a68c3 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 		/* Enable read leveling */
 		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 
+		/* Wait 1ms because of L3 timeout error */
+		udelay(1000);
+
 		/*
 		 * Enable full read and write leveling.  Wait for read and write
 		 * leveling bit to clear RDWRLVLFULL_START bit 31
-- 
2.17.1