[U-Boot] [PATCH] dts: arm: socfpga: fix socfpga_de10_nano console

[Marek Vasut]

On 4/29/19 9:50 PM, Simon Goldschmidt wrote:
> Am 29.04.2019 um 21:23 schrieb Marek Vasut:
>> On 4/29/19 8:53 PM, Simon Goldschmidt wrote:
>>> Am 29.04.2019 um 20:33 schrieb Marek Vasut:
>>>> On 4/29/19 8:32 PM, Simon Goldschmidt wrote:
>>>>> Booting this board failed as the initial console isn't found since
>>>>> commit c402e8170245 ("dts: arm: socfpga: merge gen5 devicetrees from
>>>>> linux")
>>>>>
>>>>> The uart0 devicetree entry was missing "clock-frequency =
>>>>> <100000000>:"
>>>>> since that commit
>>>>>
>>>>> Fixes: c402e8170245 ("dts: arm: socfpga: merge gen5 devicetrees from
>>>>> linux")
>>>>> Reported-by: rafael mello <rafaelmello_3 at hotmail.com>
>>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>>>>> ---
>>>>>
>>>>>    arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 1 +
>>>>>    1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
>>>>> b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
>>>>> index b620dd8dda..4be4083941 100644
>>>>> --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
>>>>> +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
>>>>> @@ -77,6 +77,7 @@
>>>>>    };
>>>>>      &uart0 {
>>>>> +    clock-frequency = <100000000>;
>>>>>        u-boot,dm-pre-reloc;
>>>>>    };
>>>>>   
>>>> Applied, thanks.
>>>
>>> Wow, that was fast!
>>>
>>>>
>>>> While at it, can we do something about Gen5 clock driver ?
>>>
>>> Which Gen5 clock driver, haha?
>>>
>>> I might find the time. Would you think the A10 driver would be a good
>>> point to start?
>>
>> For a read-only clock driver, based off DT, yes.
> 
> Well, that would be a start, using the handoff values from Quartus.
> 
> Would it make sense to convert the qts header output for gen5 to a dtsi
> format like A10? Not only the clock settings, but all information living
> in the qts directory would be better off in a devicetree.

I think so too :)

> And in addition, different FPGA configurations require different
> pinmux/iocsr configurations, which is a thing we haven't covered, yet. I
> don't want to update SPL just because an FPGA image decides to use
> loan-IO instead of a HPS GPIO...

Right ?

> However, the bindings from A10 handoff dtsi don't seem in a state to
> just copy them. (How does that handof dtsi get included anyway?)

The A10 bindings are ad-hoc mess for sure :)

(What do you mean, how?)

-- 
Best regards,
Marek Vasut